Variable-Gain Amplifier, adapted for etching into silicon.

One of the subjects which I’ve blogged about before was, The design of a variable-gain amplifier stage, that was really a variable-attenuation stage. This stage was neither suited for direct implementation with discrete components, nor on an IC. The reason for the latter detail was, that that circuit still contained coupling capacitors. Those are difficult to implement on an IC. However, I’ve done my best to do so now, in order to design a stage, which can be etched onto an IC.

My strategy for implementing a coupling capacitor was, that I’d tie the Source, Drain and Bulk electrodes of a P-channel MOSFET together on the side of the input, and use the Gate as output. However, since the N-doped well of a P-channel MOSFET also has capacitance to the substrate, I added a schematic component, that would be a ‘Semiconductor Capacitor’ according to ‘NG-SPICE‘, and the rectangular dimensions of which would just be slightly larger in each direction, than those of the MOSFET. This is meant to simulate the added, unwanted bypass-capacitor, which the preceding transistor-stage would need to be able to overpower.

This is the schematic:

Default_NM_Gain_IF_6

These are the model-cards used:

http://dirkmittler.homeip.net/text/NMOS2.mod.txt

http://dirkmittler.homeip.net/text/PMOS2.mod.txt

http://dirkmittler.homeip.net/text/JUNCCAP1.mod.txt

And this was the Net-List that defines both the circuit, and one of the simulations:

http://dirkmittler.homeip.net/text/Default_NM_Gain_IF_6.net.txt

Obviously, on an actual IC, the capacitor ‘C1′ would not exist either. Instead, a presumed preceding stage would have another transistor, that does what ‘MC1′ does in this stage.

The concept behind this circuit was, that ‘M1′ is a working inverting amplifier with reasonable voltage gain – in the ballpark of ~18, if there was no circuitry designed to make it attenuate a signal. Simply because the voltage-divider exists between ‘R2′ and ‘R3′ at the input, that goes down to ~9. Additionally, the fact that ‘R5′ follows ‘MC1′, brings the voltage-gain down to ~6, when the control-voltage is 3.0V. But, as ‘M3′ starts to conduct, it starts to feed the inverted signal from the coupling-capacitor back to the Gate, where the feedback competes with the current being fed by ‘R2′. The higher the gain of ‘M1′ is, the better the negation of the signal is, that results.

All outputs should have some sort of load indicated, so I added ‘R5′. In fact, I get the impression that NG-SPICE runs into difficulty simulating an output-voltage, if there is no load resistor. But in reality, the current that flows from the Source to the Drain of ‘M3′ will also see to it that any following, chained stages are biased as this stage was biased. (:1)

This circuit has a surprising, simulated behaviour, in that it will regulate the output voltage down, almost to zero, as the control voltage increases between 4.1V and 4.25V…

(Updated 7/30/2019, 10h20 … )

Continue reading Variable-Gain Amplifier, adapted for etching into silicon.

Hypothetical Variable Gain Amplifier

What I find is that in recent years, the term ‘Variable Gain Amplifier’ has changed in meaning, to correspond more to a ‘Variable Attenuation Stage’, after a fixed-gain amplifier. And this seems especially true, when applied to ‘IF Stages’ – ‘Intermediate Frequency Stages’ – Of a radio receiver. I’ve also observed that low-distortion technologies are preferred in recent years, as opposed to the high-distortion technologies that manufacturers were limited to, say, in the 1970s, when ‘AGC’ was first being marketed to consumers.

Yet, even with the technologies that are now available, there are sometimes added constraints. For example, if one wanted the variable-resistance component either to be optical – for lowest distortion – or, for that to be a JFET – easier to implement – then, this component might need to exist externally to an IC, just because the IC itself may be engineered only to allow for two complementary types of transistors, those being, an enhancement-mode N-channel MOSFET and an enhancement-mode P-channel MOSFET. Further, The properties of such MOSFETs can sometimes be inconvenient, in the form of high Threshold voltage, named ‘VT0′, which is the voltage required to make the transistors start to conduct. Practical values of VT0 may be more suited to logic circuits, than to the processing of low-amplitude, analog RF or IF frequencies. A thinner oxide layer for the entire IC can reduce the required VT0.

Yet, the possibility exists for even a MOSFET to operate in ‘Triode Mode’, which is a mode in which it is Not ‘Saturated’. This mode is achieved when:

VDS < VGS – VT0

The problem in trying to reach this mode seems to arise in the fact that if, VT0 is already a higher-than-desired voltage, VGS-VT0 is likely to be a lower-than-desired voltage-range, since VGS is also limited by the supply voltage.

In Triode Mode, a MOSFET effectively behaves like a variable resistor, which decreases in value as the Gate voltage continues to increase.

And so to summarize what form the task might take, to make the Variable Gain Amplifier monolithic with a MOSFET-based IC, I constructed the following, hypothetical diagram, which does not explicitly nail down what VT0 is supposed to be, nor the supply voltage:

Serge_VCR_3b.svg

 

What I seem to have noticed however, in order for the suggested IF stage to work, is that the actual signal should not have a ‘Peak Amplitude’ at the Gate of the last amplifier stage, greater than (0.1V). Yet, the feedback-loop itself, that adjusts attenuation, could play a role in keeping that peak amplitude close to (0.1V).

(Corrected 7/7/2019, 11h05 … )

Continue reading Hypothetical Variable Gain Amplifier