## Variable-gain amplifier, with good frequency response including 4MHz.

In an earlier posting, I had described a variable-gain amplifier that could be etched into a monolithic IC. But, that circuit had as its main drawback, that it would only seem to work well at a centre-frequency of ~500kHz, while most circuit designs expect Megahertz frequencies, when working in the analog domain.

The diagrams in this posting have been tested using the open-source simulation software named ‘NG-Spice’.

In order to achieve Megahertz frequency response, I needed to discover a little trick, which professional circuit designers – aka Electrical Engineers – probably already know. What the previous circuit had done, was to set (R4) to 32kΩ, while setting (R1) to 40kΩ. The reason I had done this was, the old-fashioned idea that the pull-up resistor of the amp should bisect the supply voltage, with the main transistor in series, in order to achieve maximum gain. Yet, the bias voltages were more likely to be in the vicinity of 1.8V. Thus, (R4) would bias (M2) to conduct a certain amount of current, and because both (M1) and (M4) are in saturation mode, they will both conduct the same amount of bias current between their Source and Drain, due to the resulting bias voltage at both Gates. Yet, that amount of current would cause a 1.5V voltage-drop through (R1), while causing a 1.2V voltage-drop through (R4).

Hence, with 2 voltage-levels, it was necessary to put a coupling capacitor, which in turn is a hassle on an IC.

The trick seems to be, that (R1) and (R4) can be set to the same value, so that the DC component of the Drain voltage, will equal the bias voltage. That way, as many circuits as needed can just be chained, with equal bias voltages, and No Coupling Capacitors. The bias voltage I now obtain, is (1.857V).

Additionally, I retuned the circuit, by reducing the width of (M1) and (M2) from 100μM to 25μM, which in turn reduces Drain-to-Gate capacitance, which in turn would hinder good, high-frequency response. (M4) now also has a width of 25μM, so that it can be biased in a matching way.

Yet, with the transistors so small, the output would need to be protected by that additional transistor (M4), so that to connect minor loads to it will not collapse the functioning of the main stage.

The result was, that with a control voltage of (2.0V) and a frequency of 4MHz, a gain of almost +40dB was obtained, while with a control voltage of (0.0V), a signal drop, and indeed inversion of the phase was obtained, because (M3) just bypassed (M1).

The following is the Netlist of the (2.0V) simulation:

http://dirkmittler.homeip.net/text/Default_NM_Gain_IF_13.net.txt

And these are the Modelcards of the transistors used:

http://dirkmittler.homeip.net/text/NMOS2.mod.txt

http://dirkmittler.homeip.net/text/PMOS2.mod.txt

This is an image of the schematic:

(Updated 5/29/2021, 12h15… )

## Hypothetical Variable Gain Amplifier

What I find is that in recent years, the term ‘Variable Gain Amplifier’ has changed in meaning, to correspond more to a ‘Variable Attenuation Stage’, after a fixed-gain amplifier. And this seems especially true, when applied to ‘IF Stages’ – ‘Intermediate Frequency Stages’ – Of a radio receiver. I’ve also observed that low-distortion technologies are preferred in recent years, as opposed to the high-distortion technologies that manufacturers were limited to, say, in the 1970s, when ‘AGC’ was first being marketed to consumers.

Yet, even with the technologies that are now available, there are sometimes added constraints. For example, if one wanted the variable-resistance component either to be optical – for lowest distortion – or, for that to be a JFET – easier to implement – then, this component might need to exist externally to an IC, just because the IC itself may be engineered only to allow for two complementary types of transistors, those being, an enhancement-mode N-channel MOSFET and an enhancement-mode P-channel MOSFET. Further, The properties of such MOSFETs can sometimes be inconvenient, in the form of high Threshold voltage, named ‘VT0′, which is the voltage required to make the transistors start to conduct. Practical values of VT0 may be more suited to logic circuits, than to the processing of low-amplitude, analog RF or IF frequencies. A thinner oxide layer for the entire IC can reduce the required VT0.

Yet, the possibility exists for even a MOSFET to operate in ‘Triode Mode’, which is a mode in which it is Not ‘Saturated’. This mode is achieved when:

VDS < VGS – VT0

The problem in trying to reach this mode seems to arise in the fact that if, VT0 is already a higher-than-desired voltage, VGS-VT0 is likely to be a lower-than-desired voltage-range, since VGS is also limited by the supply voltage.

In Triode Mode, a MOSFET effectively behaves like a variable resistor, which decreases in value as the Gate voltage continues to increase.

And so to summarize what form the task might take, to make the Variable Gain Amplifier monolithic with a MOSFET-based IC, I constructed the following, hypothetical diagram, which does not explicitly nail down what VT0 is supposed to be, nor the supply voltage:

What I seem to have noticed however, in order for the suggested IF stage to work, is that the actual signal should not have a ‘Peak Amplitude’ at the Gate of the last amplifier stage, greater than (0.1V). Yet, the feedback-loop itself, that adjusts attenuation, could play a role in keeping that peak amplitude close to (0.1V).

(Corrected 7/7/2019, 11h05 … )