Variable-Gain Amplifier, adapted for etching into silicon.

One of the subjects which I’ve blogged about before was, The design of a variable-gain amplifier stage, that was really a variable-attenuation stage. This stage was neither suited for direct implementation with discrete components, nor on an IC. The reason for the latter detail was, that that circuit still contained coupling capacitors. Those are difficult to implement on an IC. However, I’ve done my best to do so now, in order to design a stage, which can be etched onto an IC.

My strategy for implementing a coupling capacitor was, that I’d tie the Source, Drain and Bulk electrodes of a P-channel MOSFET together on the side of the input, and use the Gate as output. However, since the N-doped well of a P-channel MOSFET also has capacitance to the substrate, I added a schematic component, that would be a ‘Semiconductor Capacitor’ according to ‘NG-SPICE‘, and the rectangular dimensions of which would just be slightly larger in each direction, than those of the MOSFET. This is meant to simulate the added, unwanted bypass-capacitor, which the preceding transistor-stage would need to be able to overpower.

This is the schematic:

Default_NM_Gain_IF_6

These are the model-cards used:

http://dirkmittler.homeip.net/text/NMOS2.mod.txt

http://dirkmittler.homeip.net/text/PMOS2.mod.txt

http://dirkmittler.homeip.net/text/JUNCCAP1.mod.txt

And this was the Net-List that defines both the circuit, and one of the simulations:

http://dirkmittler.homeip.net/text/Default_NM_Gain_IF_6.net.txt

Obviously, on an actual IC, the capacitor ‘C1′ would not exist either. Instead, a presumed preceding stage would have another transistor, that does what ‘MC1′ does in this stage.

The concept behind this circuit was, that ‘M1′ is a working inverting amplifier with reasonable voltage gain – in the ballpark of ~18, if there was no circuitry designed to make it attenuate a signal. Simply because the voltage-divider exists between ‘R2′ and ‘R3′ at the input, that goes down to ~9. Additionally, the fact that ‘R5′ follows ‘MC1′, brings the voltage-gain down to ~6, when the control-voltage is 3.0V. But, as ‘M3′ starts to conduct, it starts to feed the inverted signal from the coupling-capacitor back to the Gate, where the feedback competes with the current being fed by ‘R2′. The higher the gain of ‘M1′ is, the better the negation of the signal is, that results.

All outputs should have some sort of load indicated, so I added ‘R5′. In fact, I get the impression that NG-SPICE runs into difficulty simulating an output-voltage, if there is no load resistor. But in reality, the current that flows from the Source to the Drain of ‘M3′ will also see to it that any following, chained stages are biased as this stage was biased. (:1)

This circuit has a surprising, simulated behaviour, in that it will regulate the output voltage down, almost to zero, as the control voltage increases between 4.1V and 4.25V…

(Updated 7/30/2019, 10h20 … )

Continue reading Variable-Gain Amplifier, adapted for etching into silicon.

NG-SPICE: Biasing the Default Transistor for Ideal Linear Voltage Gain, at 3V.

In recent days and weeks, I’ve been studying some of my own ideas, concerning the creative uses of the N-Channel, Enhancement-Mode, MOSFET. And to help me explore that subject, I’ve used An Open-Source Circuit Simulation Program called ‘NG-SPICE’. One big problem with this approach is the fact that the default transistor that the software assumes the power-user wants to use, is clearly not meant for Linear Voltage Amplification in the 100kHz-1.0Mhz frequency range, and with a 3V supply voltage. This transistor type is meant to be operated at higher voltages, and mainly, for digital uses. All the software is geared for Integrated Circuit Emphasis. But, I have looked at possible ways in which the default transistor could still be used under the conditions I’m more interested in. In theory, I could change the parameters of the transistor involved as much as I like, until I’ve made a high-speed, low-voltage transistor out of it. One problem with that is the fact that I give the software the geometry of the transistor on a chip, and the software then derives many of its assumed properties. I don’t know much about IC design, so I probably would not obtain the kind of transistor I’m looking for, if I tried to invent one.

So the question comes back, what is the best way to bias this one, arbitrary transistor-type, to act as a high-impedance amplifier under the conditions written above? And how much gain does it give me? The answer seems to be, that when connected as below, the best performance I can obtain is an Alpha of (-5.25):

Default_NM_Gain_IF_1

What I’ve also learned is, that the bias voltage associated with this circuit, with respect to ground, is (+2.14V). With respect to the supply voltage, that is (-0.86V). 3.75μV of bias current would need to flow. This information would be useful if an attempt ever came along to implement This Idea.

(Edit 7/5/2019, 17h15 : )

Doubling (VGS – VT0) of M1 would have as effect, that IDS quadruples. It would also have as effect, that equal, small changes in Gate Voltage translate into doubled changes in IDS. But, if the increase in bias current was taken into account by the circuit designer, by putting a resistor of merely 100kΩ in series with M1, thereby achieving that the supply voltage was ideally halved again as a result, then this would finally have as effect to halve the net voltage gain at the Drain of M1.

It would also have as effect, to quarter output impedance, which would be desirable from the last of a series of these stages, ending in a realistic load of some kind.

(End of Edit, 7/5/2019, 17h15.)

The Model-Card of the transistor is linked below:

http://dirkmittler.homeip.net/text/NMOS1.mod.txt

To pursue the exact subject of the earlier posting, about Variable-Gain Amplifiers, I also felt that it would be necessary to add to the circuit the components, that would transform it into a variable attenuator. And the following schematic shows how I did that:

(Updated 7/16/2019, 7h50 … )

Continue reading NG-SPICE: Biasing the Default Transistor for Ideal Linear Voltage Gain, at 3V.

NG-SPICE: Low-Powered Saw-Wave Generator

The goal of my latest exercise at using the Open-Source circuit simulation software named ‘NG-SPICE’ consisted of designing a low-powered saw-wave generator. Here were the premises of the project:

  • A train of pulses is to be taken as input, that are approximately of 1μS duration, 2V in amplitude, and that have a steady rate of recurrence of 100kHz.
  • They are to be converted into a saw-wave that has an attack as fast as the pulses are short, and which has approximately linear falloff after each input pulse.
  • One active component is a monolithic N-channel enhancement-mode MOSFET transistor with a gate size of approximately 100 microns squared – which therefore has poor qualities if compared to discrete components – but which is plausible as part of an IC with Medium Scale Integration (:2)
  • The other active component is a bipolar diode of unknown weaknesses, which has been approximated as a discrete 1N4148 switching diode.
  • The entire circuit is to operate off a 3V power supply.
  • The maximum output load is in the vicinity of 100kΩ – 40kΩ, and must not change the internal workings of this circuit block. (:1)
  • The output amplitude is to reach approximately +1V with respect to the circuit ground.

What was observed:

  • The diodes were difficult to get into a conductive state at the low pulse-voltage.
  • The chosen MOSFET makes a very poor output driver.

Saw_1

Screenshot_20190628_131425


 

The experiment seems to have been successful.

(Updated 7/3/2019, 8h35 : )

Continue reading NG-SPICE: Low-Powered Saw-Wave Generator

Another Simple Output-Amplifier, Using Discrete MOSFET Transistors

One of the facts which I’ve been writing about, is that I possess the open-source version of ‘SPICE’, that is named ‘NG-SPICE’, and that this acronym stands for ‘Simulation Program, with Integrated Circuit Emphasis’. The full, associated suite of programs allows me to edit schematic diagrams graphically, but to export ‘Netlists’, so that I can then simulate the circuit – and see if it works.

And one of the facts which I have also been contemplating, is that by default, SPICE will put transistors, which correspond to micron-sized transistors, which will therefore never be able to drive output-loads, from a hypothetical IC, unless an explicit attempt is made, to design output-buffers, which can. These output-amplifiers have as function, that they should merely follow their input voltage, but draw as little current from their respective inputs as possible – that are outputs of other, more interesting ICs – while allowing low load-resistances to be connected to their own outputs, which correspond to plausible external components, such as 100Ω load-resistors.

I had posted an earlier, conceivable design, of such an output-buffer, which had a major flaw, that I also pointed out in the preceding posting: That amplifier could only produce a range of voltages, which was a direct function of what the Gate-Source threshold voltages would be, of the component transistors used. Hence, because I had also specified low-quality, outdated MOSFET transistors with high threshold-voltages, the output-voltage-range, was also modest but reasonable. But, newer transistors will have lower threshold voltages by design, which would, oddly enough, reduce the voltage-range of that amplifier. This would be an important consideration if the transistors were not in fact discrete, but needed to be incorporated onto the IC, where low-threshold-voltage transistors are already standard. Which means, that I needed to design a better output-buffer.

So below is a better output-buffer, schematic:

buffer_2_i

And these are the SPICE definitions, of the discrete transistors which I decided to base my design on again, both enhancement-mode MOSFETs:

http://dirkmittler.homeip.net/text/2N7000.mod.txt

http://dirkmittler.homeip.net/text/BS250P.mod.txt

The main disadvantage of this latest design would be, that the transistors which I labeled ‘X2′ and ‘X3′, do in fact conduct current to their combined inputs, which makes the additional transistor ‘X1′ necessary, since this amount of current would already be excessive, to connect to an output, of any pre-existing IC circuits. But then, the advantage goes so far, that ‘X2′ now models a level-shift, which exactly mirrors the level-shift of ‘X4′, and the voltage-level-shift of ‘X3′ now mirrors ‘X5′. There is design beauty in this. But one disadvantage now is, that the Gate-Source threshold-voltage of (1) n-Channel MOSFET (2.2V) plus (1) p-Channel MOSFET (3.2V) gets subtracted from the input-voltage, so that the available voltage-range still suffers, with respect to both the supply, and the input-voltage. Input-voltage now ranges from 5.4V to approximately 12.5V, which is closer to the range of supply-voltages than what the previous circuit allowed, and the resulting output-voltages are graphed below:

screenshot_20180618_075248

(Update 06/20/2018, 0h20 : )

There is another observation which I should add:

In the days of vacuum tubes, ‘transconductance’ was measured in Amperes / Volt, and was therefore given in ‘Mhos’, which were the reciprocal of Ohms. Apparently, in modern days, the transconductance of a MOSFET, also given as its ‘KP’, is in Amperes / Volt2 . :-D This conscious design-decision must follow the real-world behavior of MOSFETs, but makes my earlier Math, of multiplying such a component-property by the series-resistance, to arrive at gain, incorrect. Gate-Source voltage-changes lead to current-changes, but greater Drain-Source voltages, lead to greater current-gain. This is good, because the actual gain of a MOSFET, reduces the apparent capacitance at its Gate.

The low-end output-voltage came into being as follows:

Continue reading Another Simple Output-Amplifier, Using Discrete MOSFET Transistors