The secret, to obtaining high-performance monolithic MOSFETs, under NG-SPICE.

One fact which I already blogged about in This Posting and This Posting, had to do with my frustration, at getting poor transistor behaviour, with enhancement-mode, N-channel MOSFETs, using the circuit simulation program called NG-SPICE.

For people who do not know, ‘SPICE’ stands for “Simulation Program, with Integrated Circuit Emphasis”. And NG-SPICE just happens to be the open-source version of it. Under Payware there are also ‘LT-SPICE’ and ‘P-SPICE’, to name a few.

Apparently, the default values which NG-SPICE puts, for the channel-length and channel-width of these MOSFETs, are just not suited for any purpose. Those are, 100μ x 100μ . And, NG-SPICE has as added drawback, that the power-user cannot just insert his customized parameters into the model-card – that defines a certain transistor-type – where they get ignored, but must put them at the end of every model-line, where the component is included in the circuit. It ‘kind of makes sense‘, since, with real ICs, the layout can be changed with every instance, but not the oxide layer thickness. But it’s also difficult to work with.

Apparently, the way to overcome that problem is, to keep the channel-widths at 100μ  , but to shorten the channel-lengths to 1μ . It gives much better results.

If the user has done this, then of course he must also recompute the optimal bias for the entire circuit, meaning the regulating resistor-values, if the goal is to keep bias-current the same. Apparently, VT0 was always a decent value (formerly ~1.8V), but the gate voltage needed to exceed this parameter by too many volts (with the  default parameters), to obtain appreciable current-flow.


 

If in saturation mode, the resulting N-channel MOSFET is to keep conducting 3.75μA, then the correct bias-voltage is ~1.7V. And the amount of available voltage-gain then, at a 3V supply voltage properly bisected, is around 18 (-). This does imply that with the new parameters, VT0 has improved by becoming smaller.

Yet, I’m still detecting an active-circuit Gate capacitance of 0.7pF. This could continue to make the design of very-high-frequency VCOs difficult. But, lower resistance values can now be chosen as components of such a VCO (at the Drain of the transistor), such as with an Astable Multivibrator, due to the better transconductance, aka ‘KP’. The constancy of the Gate capacitance strikes me as logical, since I haven’t changed the channel-width. This capacitance is usually more, with respect to the Drain, than it is, with respect to the Source or Bulk. The capacitance with respect to the Drain is likely to have been amplified, by the (inverted) voltage-gain of the stage. If that was taken out of the equation, a total of ~106fF would be apparent.

Dirk

 

The Simplest Possible Mixer, using MOSFETs.

When a curious person searches the Internet for the circuit diagrams of (electronic) mixers, there is a certain complexity of what he or she will find. Just for people who might not know, the type of mixer I’m referring to is a component which does not add two signals together – which is what the naming might seem to suggest – but rather, which multiplies two signals. In certain cases the mixer will produce output, that contains an additive component as well as a multiplied component. But it’s the multiplied component circuit designers are interested in, because that can be used:

  1. In order to produce ‘mixed frequencies’, between two input frequencies, such as between a local oscillator and a Radio Frequency, resulting in an Intermediate Frequency,
  2. In order to act as a phase discriminator, the output of which will be maximally positive or negative, when two input signals are in-phase, but the output-voltage of which will be some neutral voltage, when the input waves are 90⁰ out-of-phase with each other. In this latter case, two reasonably constant input amplitudes are assumed.

What search results will often show, is somewhat complex mixers, that require either one or two balanced inputs – meaning inputs conditioned such, that they each appear differentially between two input electrodes – and which have as advantage for being designed that way, low distortion of the wave-form(s) supplied differentially in this way.

But sometimes, low distortion is not required. For example, in the case of a PLL – a “Phase-Locked Loop” – It’s assumed that the feedback voltage changes the frequency of a VCO – a “Voltage-Controlled Oscillator” – but with the intended result that two outputs lock in some phase-position, so that the two frequencies that are inputs to the phase-discriminator will be exactly the same frequency. This latter need often arises in the design of ICs. This latter application does not require that the phase-discriminator be particularly linear, nor that its output-voltages, that become feedback voltages, be in any range other than the range which the VCO requires as input.

And so the question can arise, what the simplest way might be to design a mixer, with the added detail that both inputs are unbalanced inputs – i.e., that each input appears at one terminal, and not in an opposing way, at two terminals – and for the sake of argument, our IC might be limited to using enhancement-mode, N-channel MOSFETs as the main active component. And this would be my solution:

Coinc-Det_1.svg

The concept is very simple. If Vin1 and Vin2 are at 180⁰, then M1 and M2 don’t conduct simultaneously. Therefore, R1 and Vcc (the supply voltage) achieve maximally positive average output-voltage. If Vin1 and Vin2 are at 0⁰ phase-position, the two transistors will become conductive in a way that coincides. Therefore, this is actually a Coincidence Detector. And the average  output-voltage will be maximally negative in that case. And, if Vin1 and Vin2 are at a 90⁰ phase-position, then the average output-voltage will be somewhere between the two values mentioned before.

I suppose it should be mentioned that, if the circuit designer knows ahead of time that one of the two inputs has a much higher amplitude than the other, or a more predictable amplitude, then this usually stronger input should be fed to Vin1.

As part of a feedback loop, the output needs to be followed by a low-pass filter, that emulates an integrator over the time-constant which is the fastest, with which that feedback loop is supposed to be able to react to a change in one of the frequencies. The simplest low-pass filter consists of a resistor followed by a capacitor… (:1)

And so, when looking for a way to implement a phase-discriminator, the curious person needs to choose which of the following has greater priority:

  • The simplest circuit-design, or
  • The lowest amount of distortion.

The circuit above will certainly give the highest amount of distortion. :-P

(Updated 7/9/2019, 16h55 … )

Continue reading The Simplest Possible Mixer, using MOSFETs.

NG-SPICE: Biasing the Default Transistor for Ideal Linear Voltage Gain, at 3V.

In recent days and weeks, I’ve been studying some of my own ideas, concerning the creative uses of the N-Channel, Enhancement-Mode, MOSFET. And to help me explore that subject, I’ve used An Open-Source Circuit Simulation Program called ‘NG-SPICE’. One big problem with this approach is the fact that the default transistor that the software assumes the power-user wants to use, is clearly not meant for Linear Voltage Amplification in the 100kHz-1.0Mhz frequency range, and with a 3V supply voltage. This transistor type is meant to be operated at higher voltages, and mainly, for digital uses. All the software is geared for Integrated Circuit Emphasis. But, I have looked at possible ways in which the default transistor could still be used under the conditions I’m more interested in. In theory, I could change the parameters of the transistor involved as much as I like, until I’ve made a high-speed, low-voltage transistor out of it. One problem with that is the fact that I give the software the geometry of the transistor on a chip, and the software then derives many of its assumed properties. I don’t know much about IC design, so I probably would not obtain the kind of transistor I’m looking for, if I tried to invent one.

So the question comes back, what is the best way to bias this one, arbitrary transistor-type, to act as a high-impedance amplifier under the conditions written above? And how much gain does it give me? The answer seems to be, that when connected as below, the best performance I can obtain is an Alpha of (-5.25):

Default_NM_Gain_IF_1

What I’ve also learned is, that the bias voltage associated with this circuit, with respect to ground, is (+2.14V). With respect to the supply voltage, that is (-0.86V). 3.75μV of bias current would need to flow. This information would be useful if an attempt ever came along to implement This Idea.

(Edit 7/5/2019, 17h15 : )

Doubling (VGS – VT0) of M1 would have as effect, that IDS quadruples. It would also have as effect, that equal, small changes in Gate Voltage translate into doubled changes in IDS. But, if the increase in bias current was taken into account by the circuit designer, by putting a resistor of merely 100kΩ in series with M1, thereby achieving that the supply voltage was ideally halved again as a result, then this would finally have as effect to halve the net voltage gain at the Drain of M1.

It would also have as effect, to quarter output impedance, which would be desirable from the last of a series of these stages, ending in a realistic load of some kind.

(End of Edit, 7/5/2019, 17h15.)

The Model-Card of the transistor is linked below:

http://dirkmittler.homeip.net/text/NMOS1.mod.txt

To pursue the exact subject of the earlier posting, about Variable-Gain Amplifiers, I also felt that it would be necessary to add to the circuit the components, that would transform it into a variable attenuator. And the following schematic shows how I did that:

(Updated 7/16/2019, 7h50 … )

Continue reading NG-SPICE: Biasing the Default Transistor for Ideal Linear Voltage Gain, at 3V.

Hypothetical Variable Gain Amplifier

What I find is that in recent years, the term ‘Variable Gain Amplifier’ has changed in meaning, to correspond more to a ‘Variable Attenuation Stage’, after a fixed-gain amplifier. And this seems especially true, when applied to ‘IF Stages’ – ‘Intermediate Frequency Stages’ – Of a radio receiver. I’ve also observed that low-distortion technologies are preferred in recent years, as opposed to the high-distortion technologies that manufacturers were limited to, say, in the 1970s, when ‘AGC’ was first being marketed to consumers.

Yet, even with the technologies that are now available, there are sometimes added constraints. For example, if one wanted the variable-resistance component either to be optical – for lowest distortion – or, for that to be a JFET – easier to implement – then, this component might need to exist externally to an IC, just because the IC itself may be engineered only to allow for two complementary types of transistors, those being, an enhancement-mode N-channel MOSFET and an enhancement-mode P-channel MOSFET. Further, The properties of such MOSFETs can sometimes be inconvenient, in the form of high Threshold voltage, named ‘VT0′, which is the voltage required to make the transistors start to conduct. Practical values of VT0 may be more suited to logic circuits, than to the processing of low-amplitude, analog RF or IF frequencies. A thinner oxide layer for the entire IC can reduce the required VT0.

Yet, the possibility exists for even a MOSFET to operate in ‘Triode Mode’, which is a mode in which it is Not ‘Saturated’. This mode is achieved when:

VDS < VGS – VT0

The problem in trying to reach this mode seems to arise in the fact that if, VT0 is already a higher-than-desired voltage, VGS-VT0 is likely to be a lower-than-desired voltage-range, since VGS is also limited by the supply voltage.

In Triode Mode, a MOSFET effectively behaves like a variable resistor, which decreases in value as the Gate voltage continues to increase.

And so to summarize what form the task might take, to make the Variable Gain Amplifier monolithic with a MOSFET-based IC, I constructed the following, hypothetical diagram, which does not explicitly nail down what VT0 is supposed to be, nor the supply voltage:

Serge_VCR_3b.svg

 

What I seem to have noticed however, in order for the suggested IF stage to work, is that the actual signal should not have a ‘Peak Amplitude’ at the Gate of the last amplifier stage, greater than (0.1V). Yet, the feedback-loop itself, that adjusts attenuation, could play a role in keeping that peak amplitude close to (0.1V).

(Corrected 7/7/2019, 11h05 … )

Continue reading Hypothetical Variable Gain Amplifier