NG-SPICE: Low-Powered Saw-Wave Generator, Revisited.

This posting attempts to resolve the inadequacies of the circuit that I had already designed, using the Open-Source package ‘NG-SPICE’, and that I had described in This Earlier Posting.

Essentially there was only one problem which I was able to resolve: The bad input and output impedances of the former circuit. I now have a circuit with an input impedance of approximately 100kΩ, and an output impedance of approximately 10kΩ. A source-follower resistor for the output can be substituted where R3 is, to halve the impedance further, at the cost of also attenuating the output amplitude slightly more…

Saw_2

Screenshot_20190630_020651

These were the SPICE Model-Cards used:

http://dirkmittler.homeip.net/text/NMOS1.mod.txt

http://dirkmittler.homeip.net/text/BAS16W.mod.txt

Please do not attempt to build this circuit using discrete components. As already described in the previous, main posting, the ultra-low capacitances used in this circuit will get overpowered by stray capacitance which breadboards, wires, etc. will introduce. This circuit can only be implemented as part of a larger circuit, on the same IC. Therefore, it should only be considered hypothetical.

(Updated 7/4/2019, 8h20 … )

Continue reading NG-SPICE: Low-Powered Saw-Wave Generator, Revisited.

NG-SPICE: A Problem with the Model-Cards, and the MOSFET-Sizes, mentioned on this blog.

I’ve discovered that the version of SPICE installed on my computers is so old that the version caused a kind of malfunction. It did not allow for the specification of channel width and length on the ‘.MODEL’ line, requiring instead that these parameters be defined per-instance in the net-lists, i.e., in the circuit-files that used these components.

What I had done was to set the channel-length to 1.5u and the width to 1u, in the Model-Cards that I published on this site, hoping that to do so would standardize the behaviours of anybody trying to reproduce my results. But this had the opposite effect, in that my software failed to read the parameter at all, while the result for readers of my blog could have been that their software-version read them.

The error-messages of my software, stating that the parameters were not being read, went unnoticed somewhere amongst reams and reams of messages.

The default is 100u for both parameters, which would also be 1.0e-4 .

Dirk

 

NG-SPICE: Low-Powered Saw-Wave Generator

The goal of my latest exercise at using the Open-Source circuit simulation software named ‘NG-SPICE’ consisted of designing a low-powered saw-wave generator. Here were the premises of the project:

  • A train of pulses is to be taken as input, that are approximately of 1μS duration, 2V in amplitude, and that have a steady rate of recurrence of 100kHz.
  • They are to be converted into a saw-wave that has an attack as fast as the pulses are short, and which has approximately linear falloff after each input pulse.
  • One active component is a monolithic N-channel enhancement-mode MOSFET transistor with a gate size of approximately 100 microns squared – which therefore has poor qualities if compared to discrete components – but which is plausible as part of an IC with Medium Scale Integration (:2)
  • The other active component is a bipolar diode of unknown weaknesses, which has been approximated as a discrete 1N4148 switching diode.
  • The entire circuit is to operate off a 3V power supply.
  • The maximum output load is in the vicinity of 100kΩ – 40kΩ, and must not change the internal workings of this circuit block. (:1)
  • The output amplitude is to reach approximately +1V with respect to the circuit ground.

What was observed:

  • The diodes were difficult to get into a conductive state at the low pulse-voltage.
  • The chosen MOSFET makes a very poor output driver.

Saw_1

Screenshot_20190628_131425


 

The experiment seems to have been successful.

(Updated 7/3/2019, 8h35 : )

Continue reading NG-SPICE: Low-Powered Saw-Wave Generator

An observation about the types of logic that can be etched into silicon.

One of the questions which I had blogged about before, was that, of whether the MOSFET transistor-type inherently has 3 pins or 4. This question has a practical aspect, which I did not mention in that posting, but which is eventually interesting.

When the very high-end Electrical Engineers design chips – ICs – and specifically, when they designed earlier-generation CMOS circuitry, they were not only limited by what the fundamental properties of a MOSFET were, but also, by how many layers the machines at the time could deposit onto the chip, each of which needed to be etched and treated in a separate, very precise stage of the manufacturing process. This is why I find it helpful that the WiKiPedia article I just linked to, displays a CMOS circuit, and how it was originally implemented, as their explanation of the subject.

What the reader may take note of, is the example of the P-channel MOSFET, which consists of a Source, a Drain, a Gate, a Bulk Electrode, and a Substrate. The role of this Bulk Electrode needs to be given some special attention. Because of the way these transistors were in fact etched, additional, unintentional, “parasitical” transistors could form, for example, a ‘hidden’ PNP, Bipolar Transistor, between the Drain, the N-doped well, and the P-doped substrate. In theory, if the N-doped well became negative enough, with respect to either the potential of the substrate or that of the P-doped Drain, then this parasitical transistor could become forward-biased, and start to conduct and amplify its own currents, with the Drain acting as Emitter, with the N-doped well acting as Base, and with the Substrate acting as Collector. The same thing could theoretically also happen, with the P-doped Source acting as Emitter instead.

The way this behaviour was prevented, was by connecting the N-doped well to the positive supply voltage, and always keeping the P-doped substrate connected to the negative supply voltage. This formed a so-called ‘isolation diode’, and prevented the parasitical transistor from becoming active.

Well in the circuit which I had clicked together using the NG-SPICE software, each MOSFET was a 4-pin component, and my main point of attention was on how to get my software to acknowledge whatever circuits I had entered. If the circuit in question needed to be etched, using the original technology, then the bulk electrode of each MOSFET would also need to be connected either to the negative supply voltage in the case of an N-channel MOSFET, or to the positive supply voltage in the case of a P-channel MOSFET. Hence, the existence of 3-pin MOSFETs was not due to whether the transistor-type was inherently so, but just due, to how certain forms of the technology were being manufactured, as consisting of a minimal number of layers. And this also forced the inclusion of the transistors as having 3 electrodes into certain schematics, just because their implementors could not implement the 4-electrode variety in certain cases – and in fact, often.

If the schematic was ever to be etched into silicon, as I drew it in my earlier posting, and as NG-SPICE was simulating it, then at the very least, a much-more recent form of Integrated Circuit would need to be used as architecture. And then one problem which would next follow would be, that this more-recent architecture also makes the transistors much smaller, such as 40 Nanometre or 10 Nanometre technology (?), which would result in individual transistors that cannot handle the amounts of current which discrete circuits require, so that the complications of driving output pins would become more pronounced.

One reason for which I did not elaborate this fact in my past posting was the realization that I’d have to link to yet-another WiKi-page in order to do so, and that WiKiPedia articles get edited from time to time. I did not know that the WiKi would keep the traditional layout of the CMOS layers a part of their article for so long.

Continue reading An observation about the types of logic that can be etched into silicon.