In an earlier posting, I had described a variable-gain amplifier that could be etched into a monolithic IC. But, that circuit had as its main drawback, that it would only seem to work well at a centre-frequency of ~500kHz, while most circuit designs expect Megahertz frequencies, when working in the analog domain.
The diagrams in this posting have been tested using the open-source simulation software named ‘NG-Spice’.
In order to achieve Megahertz frequency response, I needed to discover a little trick, which professional circuit designers – aka Electrical Engineers – probably already know. What the previous circuit had done, was to set (R4) to 32kΩ, while setting (R1) to 40kΩ. The reason I had done this was, the old-fashioned idea that the pull-up resistor of the amp should bisect the supply voltage, with the main transistor in series, in order to achieve maximum gain. Yet, the bias voltages were more likely to be in the vicinity of 1.8V. Thus, (R4) would bias (M2) to conduct a certain amount of current, and because both (M1) and (M4) are in saturation mode, they will both conduct the same amount of bias current between their Source and Drain, due to the resulting bias voltage at both Gates. Yet, that amount of current would cause a 1.5V voltage-drop through (R1), while causing a 1.2V voltage-drop through (R4).
Hence, with 2 voltage-levels, it was necessary to put a coupling capacitor, which in turn is a hassle on an IC.
The trick seems to be, that (R1) and (R4) can be set to the same value, so that the DC component of the Drain voltage, will equal the bias voltage. That way, as many circuits as needed can just be chained, with equal bias voltages, and No Coupling Capacitors. The bias voltage I now obtain, is (1.857V).
Additionally, I retuned the circuit, by reducing the width of (M1) and (M2) from 100μM to 25μM, which in turn reduces Drain-to-Gate capacitance, which in turn would hinder good, high-frequency response. (M4) now also has a width of 25μM, so that it can be biased in a matching way.
Yet, with the transistors so small, the output would need to be protected by that additional transistor (M4), so that to connect minor loads to it will not collapse the functioning of the main stage.
The result was, that with a control voltage of (2.0V) and a frequency of 4MHz, a gain of almost +40dB was obtained, while with a control voltage of (0.0V), a signal drop, and indeed inversion of the phase was obtained, because (M3) just bypassed (M1).
The following is the Netlist of the (2.0V) simulation:
And these are the Modelcards of the transistors used:
This is an image of the schematic:
(Updated 5/29/2021, 12h15… )