Simulating Lossy or Custom Transmission Lines, using NG-Spice.

One of the fun things that can be done using the Open-Source circuit-simulator ‘NG-Spice’ is, that transmission lines can be simulated, with the parameters ‘Z0′ and ‘TD’, which stand for the characteristic impedance, and the delay down the length of the transmission line. However, what some people have noticed, and recorded as a bug, elsewhere on the Web, is, that such transmission lines will appear to have ideal behaviour right down to ‘DC frequencies’.

Rather than to think of this as a bug, I’d categorize this as the behaviour, that if the ‘RefDes’ of the transmission line begins with the letter ‘T’, NG-Spice will always simulate a lossless transmission line.

What some people might prefer is, to simulate a lossy transmission line. And When using NG-Spice, this capability is available, but hidden. Basically, NG-Spice uses the same simulation engine, to simulate the Netlists, that other versions of Spice will use. But, the Open-Source version will be lacking in GUI support, as well as in the available libraries of components.

The key to understanding, how to simulate a lossy transmission line, is, that NG-Spice will only process them as being a different type of component, if their reference descriptor begins with the letter ‘O’. This is similar to how NG-Spice will require that the ‘RefDes’ begin with the letter ‘X’, if what is to be simulated, is some sort of sub-circuit. But, because this will stem from a modelcard, the model of the transmission line will actually need to be specified within the Schematic Editor, as the Value of the component, for which there also needs to be a Model entry in the schematic, that points to the file, which will define the model. This Model entry will have a reference descriptor, beginning with the letter ‘A’…

(Updated 6/07/2021, 2h25… )

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Classical, impedance-quadrupling BalUn transformer.

Some readers might ask themselves, ‘What the heck is a Balun transformer?’ And the answer is that, in certain high-frequency applications, this term gets used for a Balanced-to-Unbalanced (impedance-matching) transformer, often implemented as a transmission-line transformer. One common place they did get used in years gone by was, to allow people to connect 300Ω twin-lead TV antenna cable, to the 75Ω coax inputs of more-recent TVs. Actually, what was inside those little adapters was, a toroidal ferrite core, with a piece of sheet-metal (probably aluminum) stamped around it in a clever way, so that this stamped sheet of metal also acted as the ~windings~ of the transformer.

Really, this type of transformer does the same thing that an ‘autotransformer’ does, only, at much higher frequencies. If the reader is picturing a (center-tapped) autotransformer with many windings, then he or she should also picture how many implicit, internal capacitors those have (between the windings), and how capacitors become increasingly conductive, at higher frequencies… Traditional, wound transformers start to become useless well before 100MHz has been reached.

If people look this subject up elsewhere on the Web, They might find diagrams of various types of transmission-line transformers. But, it’s easy to get confused about the way those need to be connected, so that one possible result could be, a transformer that does not work correctly. For that reason, I have just reconstructed how I remember them to have been configured in the past:




I suppose that another piece of possibly related trivia could be, that an impedance of, say, 150Ω, connected to a voltage of zero, is equivalent to 300Ω, connected to a relative voltage of (-1). Another related assumption is, that such transmission lines are indeed wound on effective ferrite cores, capable of choking their net current to zero.


Now, there’s another, related application of transmission-line transformers, which could be, that a number of transistorized output drivers might only be able to handle some higher (load-) impedance (each), but that the goal is to combine their amperage, so that a divided output-impedance also results, at minimal waste of energy. Additionally, some small mismatch in the outputs could be expected, which should be absorbed, and not result in reflected waves…

(Updated 6/02/2021, 9h15… )

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Variable-gain amplifier, with good frequency response including 4MHz.

In an earlier posting, I had described a variable-gain amplifier that could be etched into a monolithic IC. But, that circuit had as its main drawback, that it would only seem to work well at a centre-frequency of ~500kHz, while most circuit designs expect Megahertz frequencies, when working in the analog domain.

The diagrams in this posting have been tested using the open-source simulation software named ‘NG-Spice’.

In order to achieve Megahertz frequency response, I needed to discover a little trick, which professional circuit designers – aka Electrical Engineers – probably already know. What the previous circuit had done, was to set (R4) to 32kΩ, while setting (R1) to 40kΩ. The reason I had done this was, the old-fashioned idea that the pull-up resistor of the amp should bisect the supply voltage, with the main transistor in series, in order to achieve maximum gain. Yet, the bias voltages were more likely to be in the vicinity of 1.8V. Thus, (R4) would bias (M2) to conduct a certain amount of current, and because both (M1) and (M4) are in saturation mode, they will both conduct the same amount of bias current between their Source and Drain, due to the resulting bias voltage at both Gates. Yet, that amount of current would cause a 1.5V voltage-drop through (R1), while causing a 1.2V voltage-drop through (R4).

Hence, with 2 voltage-levels, it was necessary to put a coupling capacitor, which in turn is a hassle on an IC.

The trick seems to be, that (R1) and (R4) can be set to the same value, so that the DC component of the Drain voltage, will equal the bias voltage. That way, as many circuits as needed can just be chained, with equal bias voltages, and No Coupling Capacitors. The bias voltage I now obtain, is (1.857V).

Additionally, I retuned the circuit, by reducing the width of (M1) and (M2) from 100μM to 25μM, which in turn reduces Drain-to-Gate capacitance, which in turn would hinder good, high-frequency response. (M4) now also has a width of 25μM, so that it can be biased in a matching way.

Yet, with the transistors so small, the output would need to be protected by that additional transistor (M4), so that to connect minor loads to it will not collapse the functioning of the main stage.

The result was, that with a control voltage of (2.0V) and a frequency of 4MHz, a gain of almost +40dB was obtained, while with a control voltage of (0.0V), a signal drop, and indeed inversion of the phase was obtained, because (M3) just bypassed (M1).

The following is the Netlist of the (2.0V) simulation:

And these are the Modelcards of the transistors used:


This is an image of the schematic:




(Updated 5/29/2021, 12h15… )

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Hypothetical schema for sampling maxima and minima of a continuous analog signal.

I have just examined a hypothetical application of modern IC technology. What’s already available out-of-the-box is, that for every Analog – Digital Conversion, a single value can be generated. And today’s chips allow this to happen at 100Msps, resulting in a bandwidth of 50MHz. But for some reason, the goal might be desired, that for each of these conversions, a pair of values is generated, that accurately reflect what the maximum and minimum analog value was. As a result, a hypothetical ~oscilloscope~ could display a column of pixels, with one X-coordinate, instead of just one pixel, indicating one Y-coordinate. And so, this is the first of 3 diagrams I came up with:




My assumption is, that a 100Msps A/D Conversion will follow each of the above circuit’s 2 outputs…

(Updated 5/27/2021, 10h30… )

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