The secret, to obtaining high-performance monolithic MOSFETs, under NG-SPICE.

One fact which I already blogged about in This Posting and This Posting, had to do with my frustration, at getting poor transistor behaviour, with enhancement-mode, N-channel MOSFETs, using the circuit simulation program called NG-SPICE.

For people who do not know, ‘SPICE’ stands for “Simulation Program, with Integrated Circuit Emphasis”. And NG-SPICE just happens to be the open-source version of it. Under Payware there are also ‘LT-SPICE’ and ‘P-SPICE’, to name a few.

Apparently, the default values which NG-SPICE puts, for the channel-length and channel-width of these MOSFETs, are just not suited for any purpose. Those are, 100μ x 100μ . And, NG-SPICE has as added drawback, that the power-user cannot just insert his customized parameters into the model-card – that defines a certain transistor-type – where they get ignored, but must put them at the end of every model-line, where the component is included in the circuit. It ‘kind of makes sense‘, since, with real ICs, the layout can be changed with every instance, but not the oxide layer thickness. But it’s also difficult to work with.

Apparently, the way to overcome that problem is, to keep the channel-widths at 100μ  , but to shorten the channel-lengths to 1μ . It gives much better results.

If the user has done this, then of course he must also recompute the optimal bias for the entire circuit, meaning the regulating resistor-values, if the goal is to keep bias-current the same. Apparently, VT0 was always a decent value (formerly ~1.8V), but the gate voltage needed to exceed this parameter by too many volts (with the  default parameters), to obtain appreciable current-flow.


 

If in saturation mode, the resulting N-channel MOSFET is to keep conducting 3.75μA, then the correct bias-voltage is ~1.7V. And the amount of available voltage-gain then, at a 3V supply voltage properly bisected, is around 18 (-). This does imply that with the new parameters, VT0 has improved by becoming smaller.

Yet, I’m still detecting an active-circuit Gate capacitance of 0.7pF. This could continue to make the design of very-high-frequency VCOs difficult. But, lower resistance values can now be chosen as components of such a VCO (at the Drain of the transistor), such as with an Astable Multivibrator, due to the better transconductance, aka ‘KP’. The constancy of the Gate capacitance strikes me as logical, since I haven’t changed the channel-width. This capacitance is usually more, with respect to the Drain, than it is, with respect to the Source or Bulk. The capacitance with respect to the Drain is likely to have been amplified, by the (inverted) voltage-gain of the stage. If that was taken out of the equation, a total of ~106fF would be apparent.

Dirk

 

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