Essentially there was only one problem which I was able to resolve: The bad input and output impedances of the former circuit. I now have a circuit with an input impedance of approximately 100kΩ, and an output impedance of approximately 10kΩ. A source-follower resistor for the output can be substituted where R3 is, to halve the impedance further, at the cost of also attenuating the output amplitude slightly more…
These were the SPICE Model-Cards used:
Please do not attempt to build this circuit using discrete components. As already described in the previous, main posting, the ultra-low capacitances used in this circuit will get overpowered by stray capacitance which breadboards, wires, etc. will introduce. This circuit can only be implemented as part of a larger circuit, on the same IC. Therefore, it should only be considered hypothetical.
(Updated 7/4/2019, 8h20 … )
(Update 7/1/2019, 13h50 : )
A question which a reader might have about this version of the circuit would be, ‘Dirk was previously using a 1nF capacitor as the main component. Why did he reduce that to 50pF?’ Doing so makes attempts to test the circuit using discrete components impossible, while before, if attempted by a hobbyist, the success would merely have been improbable.
The answer to that question had to do with the realization that the first version of this circuit, which I explained fully in the posting I linked to above, had an effective input impedance of 1kΩ. It’s possible to put a voltage-following transistor before the input of the previous circuit – which happens to be what I did – that has high input-impedance itself. But then, when that transistor is driving the voltage of C2 to its peak, M4 will only be drawing the equivalent current from the power supply. Thus, the loading of the power supply would momentarily become the equivalent of a 1kΩ resistor.
The context of this exercise was, that this was to become a plausible sub-circuit of a larger one, to be put on a low-power IC, which should just not put loads as heavy as 1kΩ on the power-supply either, especially in the form of 1μS pulses.
So, by dividing the value of C2 by 20, I’ve achieved that the maximum load this circuit will put on the power supply, will be in the form of a virtual, 20kΩ resistor, for 1μS periods, spaced 10μS apart…
50pF capacitors are also easier to implement on an IC than 1nF capacitors would have been, and the corresponding diodes closer to IC diodes. In the circuit simulation above, I used the discrete ‘BAS16W’ diode’s data-sheet, which also specifies its capacitance as a mere ~2pF, knowing that an eventual diode would be even tinier. Before, I was using the ‘1N4148′ switching diode’s, which, if used, would have required more robust voltages and currents, to be made to switch on. And then, that earlier diode also has higher capacitance itself, than the current one is specified to have.
I should also reiterate what I wrote in the posting I linked to above, which was, that the transistor-type assumed by my software is far too weak. NG-SPICE defaults to a MOSFET with a 15nM Oxide-Layer Thickness, together with Gate-Regions (areas on the chip) that would measure 100×100 μM. NG-SPICE then performs a Level-8 simulation of the MOSFET, which derives many other parameters from this basic geometry, including what the threshold voltage will be… As described, I have changed that geometry for M3 and M4 specifically, to a channel-width of 500μM, to get the MOSFET to conduct better, when given the same set of input-voltages. Chips are also possible that have thinner oxide-layers, which will result in lower threshold-voltages, but my assumption is that the oxide-layer can only be changed for an entire chip, while the layout can be changed per transistor. And so, I kept that at 15nM for the sake of this exercise.
Later versions of NG-SPICE than my own allow the Area of the transistor to be stated in its definition, in the Model-Card linked to above. But my own version of this software requires that it be specified with each instance, in the circuit, when not at the software’s default. And, Doing the latter required that I edit the Net-List which ‘GSpiceUI’ generated, using a text-editor, and before reopening GSpiceUI, to run the resulting simulation.
Even when given a channel-width of 500μM, M4 will only develop a resistance between its Source and its Drain, which does not fully go below 20kΩ. And so, to keep a 1nF value as C2 would have remained infeasible, even when using M4 as the input amplifier. And, to make the width of a MOSFET more than 5x its channel-length, seems to cause phenomena to take place, that limit how ‘hard’ its current-handling capabilities can become, which I assume that NG-SPICE was predicting correctly, but which I was just learning about. So the only variation of this transistor which I ended up considering was, ‘W=500u L=100u’ .
(Update 7/1/2019, 17h00 : )
Why the range of voltages across C2 is only a fraction of the applied signal voltage:
Together with the fact that both M3 and M4 are only connected to act as voltage-followers, not as gain-stages, there are two major factors attenuating the voltage-range across C2:
If M4 forms a hypothetical resistor of 20kΩ, when connected with the 50pF capacitor C2, this implies a time-constant of 1μS. It does not imply that C2 will charge fully within that amount of time! It implies an exponential decay of the voltage ‘across the virtual resistor’ which reaches (e-1) times the applied voltage, after that amount of time. This ‘fraction’ is 0.3679. Therefore, the maximum voltage across C2 would only reach 63% of the original voltage for that reason. But in addition to that, if the hypothetical resistor is connected in series with the explicit, 40kΩ resistor R4, this implies a voltage-divider that achieves 2/3 the applied voltage again. When these two sources of attenuation are combined, the result should be a voltage-range that is only 42% of the applied signal-voltage.
Another source of attenuation is the fact that I chose C1 only to have 500pF, so that when it forms a bridge with C2, another 10% of attenuation will take place. And why did I make C1 so small? Because it needs to discharge across R4, which has 40kΩ, over the course of several pulses, that are 10μS apart, and so that the pair of diodes will continue to work properly. In fact, those two components have an implied time-constant of 20μS. I could not make R4 larger, or make M4 more conductive, and so, there exist several sources of attenuation.
If I made the capacitors smaller, then, even as part of an IC, the other components, i.e., D1, D2 and M3, would add too many capacitively coupled currents, that would start to dominate the behaviour of the circuit, which is supposed to be controlled by C2. And even the simulation software NG-SPICE displayed this fact.
Contrarily, C3 and R5 were chosen to be ‘arbitrarily high’, given the fact that the DC impedance of the input gate of a MOSFET is effectively infinite, and that M4 needed to be biased to conduct for most of the duration of the input-pulse. Subtracted from the supply voltage of 3V, the voltage drop across D1 (0.5V) leaves approximately the threshold voltage of these MOSFETs.
Theoretically I could have connected R5 to the supply voltage. Because the amount of DC voltage across C1 is irrelevant, this would simply have caused the voltage at the Source of M4 to follow (partially), and more bias-current to flow through R4 and M4. Connecting it as shown causes the circuit to draw less unnecessary current from the supply.
(Update 7/1/2019, 23h40 : )
The following is the Net-List which defines both the circuit and the simulation, corresponding to the graphics at the beginning of this posting:
As it turns out, the way to overcome the limitations of decreasing voltages, when these sorts of circuits are chained, is to make at least some stages inverting amplifiers. And as it happens, the output driver I chose, M3, is a good candidate to be reconfigured in this way. The graphics below describe the result I obtain when I do that:
What the reader may notice is that:
- I needed to increase R2 slightly, so that the average voltage across C2 increases, just so that M3 doesn’t come as close to being ‘biased off’ as it did before,
- I needed to connect a hefty 100pF capacitor between the Drain and the Source of M3.
This latter measure was necessary because when I increased the channel-width of this MOSFET five-fold, NG-SPICE also recomputed that the capacitance between its Gate and the Drain increased five-fold. This initially resulted in voltage-spikes at the output, during the upwards swing of the voltage on C2 (where the output voltage is supposed to be decreasing), but was also adding itself to the capacitance which C2 appeared to have, with the gate of M3 connected in parallel (which, in turn, was limiting the maximum voltage-range on C2 that I could obtain).
And this is a link to the Net-List, of the second circuit described in this blog, which also defines the ensuing simulation:
Now, I suppose that the next question to ask would be, ‘What could be done to improve the linearity of the output of this circuit-block, if high linearity was required?’ And the general answer to that question in the design of analog circuits would be, to introduce negative feedback.
Because the voltage-swing at the Gate of M3, in the previous version of the circuit, was only 0.5V, I can compute that the average current flowing from C2 during its almost-linear period of discharge is approximately 2.5μA, while the long-term swing of output voltages from the circuit block is approximately 1V, it might seem that an appropriate feedback-resistor between the Drain and the Gate of M3 should have about 400kΩ. But it must be remembered that such a resistor needs to be isolated from the DC voltage-difference, between those two electrodes of M3, by a series capacitor, which should have approximately 25pF, so that the two will imply a time-constant of about 10μS, which is also the period of recurrence, of the pulse-sequence. However, such a feedback resistor would actually introduce non-linearity, instead of better linearity.
Instead, If the starting assumption was accepted that the discharge of C2 was already linear, as well as that the final output voltage at the Drain of M3 had a linear slope in the opposite direction, then, inserting purely a feedback capacitor between the Drain and Gate of M3 should have as effect, a constant current flowing through this added capacitor. Which should preserve, a constant current flowing from C2… And it’s seen that the previous voltage-gain of M3 appeared to be (-2).
Well, if only such a feedback capacitor was added, then the previous circuit would also need to be compensated for it in some way, in order to generate the same output voltage-swing. As it happens, because the voltage at the Drain of M3 is now proportionally opposite of that at its Gate, adding a certain amount of capacitance there, gets multiplied, as the effective capacitance added to C2.
(Edit 7/2/2019, 2h15 :
This happens with the correct polarity because while the voltage across C2 is decreasing, positive current is flowing from it to the node it’s connected to (opposite ground). Simultaneously, the output voltage of the circuit block will be increasing, so that positive current will also flow from the feedback capacitor, to the same node. The ratio of the sum of these currents to the negative rate of voltage-change, defines the effective, combined capacitance.
If the correct amount of feedback capacitance was added, then the result of that would be that the earlier C2 could be reduced to zero, and C2 thus replaced by this feedback capacitor, which could become the new C2.
This magic result seems to happen when the feedback capacitor added has 10pF. Why the strange ratio? One might expect that a value of (50/3=16.6pF) would work. I suspect that the workable ratio arises because significant capacitance already existed within this MOSFET – close to 6pF x2 – and the real capacitance present where the earlier C2 was, was never really 50pF, with M3 connected in parallel. And so the following two graphics show what the result is, when the feedback capacitor has become the new C2:
I was able to obtain the same range in output voltages.
The following link to a Net-List defines both this third circuit, and its simulation:
(Update 7/3/2019, 14h35 : )
According to the latest version of the circuit, the amount of ‘constant current’ flowing through R1 is 3.33μA, which assumes a Gate voltage at M1 and M2 of 2.75V, which would be 0.25V greater than the apparent threshold voltage. The average, voltage-stabilizing current flowing through R2 is 1.375μA, which puts me close to my initial goal, of having 1/3 the discharging current flow through R2, and having 2/3 that current defined by R1.
From the added facts that the voltage-range at the Gate of M3 is 0.8V, and that the decay-interval is 10μA, it follows that the total effective, virtual capacitance at the Gate of M3 is 58.85pF.
What the reader may also notice is that although the saw-wave seems to have good linearity over most of its essential period, near the peak, the output-voltages seem to experience non-linearity. In my opinion this is due to the Gate voltage of M3 venturing too low, as a result of the inverted saw-wave present there, which is getting too close to the threshold voltage of M3, at which time the conductivity of M3 will no longer respond adequately to changes in its Gate voltage.
This can be remedied by making R2 slightly higher again, causing less non-linear current to flow through it. Since proper operating parameters have been established for this latest version of the circuit, doing so will only cause the average Gate voltage of M3 to increase slightly, so that M3 will constantly be ‘biased on’.
I suggest that the reader try applying ‘R2=2200k’ and correspondingly, ‘R5=9k’ … Doing so increases the voltage-gain of M3, as well as the virtual capacitance acting at its Gate, and lengthens the period of the saw-wave, that is linear.
(Update 7/4/2019, 8h20 : )
As a summary, the previous exercise was assuming an input pulse-width of 1μS, and a period of recurrence of 10μS. To satisfy my own curiosity, I have created a derived exercise, with an input pulse-width of 20μS and a period of recurrence of 100μS. In order to realize this, I wanted an effective capacitance of 500pF. Thus, I calculated my feedback capacitor as (500pF / 3 – 6 = 160pF). And I achieved success:
This time, the oscilloscope-like plot reveals the negative feedback in action much better, in that the Gate voltage of M3 is much more non-linear, even though the output voltage is closer to linear, especially within a sub-section of the period.
The way to compensate the circuit for potential, longer pulse-widths, is to place a resistor is series with the Drain of M4.