The goal of my latest exercise at using the Open-Source circuit simulation software named ‘NG-SPICE’ consisted of designing a low-powered saw-wave generator. Here were the premises of the project:
- A train of pulses is to be taken as input, that are approximately of 1μS duration, 2V in amplitude, and that have a steady rate of recurrence of 100kHz.
- They are to be converted into a saw-wave that has an attack as fast as the pulses are short, and which has approximately linear falloff after each input pulse.
- One active component is a monolithic N-channel enhancement-mode MOSFET transistor with a gate size of approximately 100 microns squared – which therefore has poor qualities if compared to discrete components – but which is plausible as part of an IC with Medium Scale Integration (:2)
- The other active component is a bipolar diode of unknown weaknesses, which has been approximated as a discrete 1N4148 switching diode.
- The entire circuit is to operate off a 3V power supply.
- The maximum output load is in the vicinity of 100kΩ – 40kΩ, and must not change the internal workings of this circuit block. (:1)
- The output amplitude is to reach approximately +1V with respect to the circuit ground.
What was observed:
- The diodes were difficult to get into a conductive state at the low pulse-voltage.
- The chosen MOSFET makes a very poor output driver.
The experiment seems to have been successful.
(Updated 7/3/2019, 8h35 : )
(As of 6/28/2019 : )
SPICE Model-Cards used in the simulation:
(Update 6/29/2019, 15h10 : )
The behaviour of this circuit can be improved if the type of MOSFET is changed to a low-voltage variety, therefore with a low threshold voltage, and that also conducts higher amounts of current at those low, ‘turned-on’ gate voltages. As it stands, the input impedance will seem to be around 1kΩ, while the output impedance will be around 40kΩ. Generally, circuit-blocks are supposed to have lower output impedance than input impedance, precisely so that as many of them can be chained, as the situation requires.
The type of MOSFET required is said to exist. However, I’m not motivated to try finding the SPICE Model-Card for the ‘NX3008NBKW’ because that would be a discrete component, while this project had as assumption, that all the components are finally part of the same chip. There are other components which I could insert, such as a bipolar transistor, which would solve the problem well, except for the idea that all this is supposed to work as part of a single chip…
One of the side effects that would follow, if every MOSFET in my circuit was an NX3008NBKW, is higher capacitance-values associated with the components themselves. As it stands, I’d have a 1nF capacitor working with two 22.5kΩ resistors, and with microsecond pulse-widths. If a hobbyist was to try to build this circuit from discrete components, he’d soon discover that stray capacitance, as well as parasitical capacitance of those chosen components, overpower what the 1nF capacitor is supposed to be doing.
Yet, if everything was part of a single chip, this combination of capacitance, resistances, and frequencies should work.
The SPICE Model-Card for the NX3008NBKW can be found, as they can for most existing components these days, but they’d need to be inserted into a schematic as a 3-pin sub-circuit, with my software, as a ‘SUBCKT_NMOS’, and given a Reference Descriptor that begins with an ‘X':
And while that Model-Card does specify a Gate Capacitance of 31.88 pF – under the parameter ‘CGS’ – given discrete packages and wires, I’m doubtful that those values correspond accurately to what the stray capacitance would be. But, a value of 32pF can certainly be simulated!
(Update 6/29/2019, 17h25 : )
An explanation of the circuit:
When a voltage-swing is transmitted by the coupling capacitor C1, the activation of diodes D1 and D2 adds an amount of charge to capacitor C2, which is determined by the pulse-amplitude and the capacitance of C2.
Simultaneously, MOSFETs M1 and M2 act as a current-mirror when ideally biased, so that the current flowing through R1 equals some amount of current to be drawn from C2. The constancy of the power source is supposed to keep this amount of current constant, and the resulting rate of discharge of C2, linear.
But, if that was the only current causing C2 to discharge, then an eventual outcome would be that it does not equal the cumulative rate with which C2 is being charged, by a longer sequence of pulses. The voltage on C2 would therefore tend to increase steadily, or to decrease until the bottom of the saw-wave is cut off. Therefore, R2 has been added as a voltage-stabilizing component, which also adds some on-linearity to the saw-wave.
R1 and R2 have been chosen so that approximately, R2 conducts 1/3 and R1 conducts 2/3 of the amount of current that would be consistent with a pulse-amplitude of 2V, and with a falloff that takes 10μS to complete, and with a supply voltage of 3V. This gives equal resistance values by accident. (:3)
Also, M1 and M2 will fail to act as a very good current-sink because each MOSFET requires an unusually high fraction of the supply voltage at its gate to turn on. Hence, this high threshold voltage is a component characteristic which does not only affect M3 adversely.
M3 and R3 are an abbreviation for a voltage-follower, that will need to be re-implemented in some way before a practical circuit will result.
The amount of charge which the input pulse adds to C2, together with the capacitance of C2 and the duration of the pulse, give an estimation of the maximum input impedance of the circuit as 1kΩ. However, when connected to a controlled voltage-curve, the peak of current is drawn at the rise of the input pulse, instead of over its duration. Therefore, theoretically, to avoid issues in how this input loads a potential output – of a preceding circuit – a 1kΩ resistor should be connected in series with C1. However, doing that, or decreasing the value of R3 to something like 40kΩ, will put an end to ‘the magical result’, that 1V is in fact achieved as the output amplitude. I’ve tried it.
(Update 6/29/2019, 20h15 : )
I’ve discovered that the version of SPICE installed on my computers is so old that the version caused a kind of malfunction. It did not allow for the specification of channel width and length on the ‘.MODEL’ line, requiring instead that these parameters be defined per-instance in the net-lists, i.e., in the circuit-files that used these components.
What I had done was to set the channel-length to 1.5u and the width to 1u, in the Model-Cards that I published on this site, hoping that to do so would standardize the behaviours of anybody trying to reproduce my results. But this had the opposite effect, in that my software failed to read the parameter at all, while the result for readers of my blog could have been that their software-version read them.
The default is 100u for both parameters, which would also be 1.0e-4 .
In the same vein, an oxide thickness of less than 15n could be specified, resulting in a monolithic MOSFET that has lower gate threshold voltage. But then this would correspond to a guessed parameter. Even though an IC with such a non-default oxide thickness can be manufactured, the answer to whether any truly manufactured ICs use that oxide thickness, is likely to be No.
What I can do in a less suspect manner, is to edit the Netlist in a Text Editor, such that one specific MOSFET – M3 – has been given a channel-width of 500 microns instead of 100, with the result that for any given difference, between Gate-Source Voltage and the implicit technology’s Threshold Voltage, 5x as much current will flow through M3. But then, a predictable side effect will be that negative feedback sets in because more current flowing through R3 will also raise the Source Voltage of M3, thus ‘pinching off’ the current. But then this can lead to a lower output impedance, just not to greatly improved output amplitudes, as the screen-shot below demonstrates:
So the peak voltage is now 1.38 Volts instead of 1.00V . Yet, this voltage will be more stable when a greater load is connected to the Source of M3…
(Update 6/30/2019, 2h50 : )
I have created a second circuit as a follow-up to this one, documented in This Posting, in which I assume that the same Oxide Layer Thickness is to be applied, but that the Gate Width of some specific MOSFETs can be changed in the Net-Lists. The result is properly managed impedance values at least.
(Update 7/3/2019, 8h35 : )
At first, I had made the assumption that the voltage at the gate of M1 and M2 would only be 2.5V. But later experiences with the simulation indicate this voltage to be 2.75V. This means that the voltage across R1 is only half of what it’s supposed to be, and the amount of constant current likewise. But the way the circuit is designed this only causes the average voltage at the gate of M3 to increase slightly, so that the average current flowing through R2 also increases, to make up for the error in the current flowing through the current mirror.
R2 does after all act as a voltage-regulating resistor.