An observation about the types of logic that can be etched into silicon.

One of the questions which I had blogged about before, was that, of whether the MOSFET transistor-type inherently has 3 pins or 4. This question has a practical aspect, which I did not mention in that posting, but which is eventually interesting.

When the very high-end Electrical Engineers design chips – ICs – and specifically, when they designed earlier-generation CMOS circuitry, they were not only limited by what the fundamental properties of a MOSFET were, but also, by how many layers the machines at the time could deposit onto the chip, each of which needed to be etched and treated in a separate, very precise stage of the manufacturing process. This is why I find it helpful that the WiKiPedia article I just linked to, displays a CMOS circuit, and how it was originally implemented, as their explanation of the subject.

What the reader may take note of, is the example of the P-channel MOSFET, which consists of a Source, a Drain, a Gate, a Bulk Electrode, and a Substrate. The role of this Bulk Electrode needs to be given some special attention. Because of the way these transistors were in fact etched, additional, unintentional, “parasitical” transistors could form, for example, a ‘hidden’ PNP, Bipolar Transistor, between the Drain, the N-doped well, and the P-doped substrate. In theory, if the N-doped well became negative enough, with respect to either the potential of the substrate or that of the P-doped Drain, then this parasitical transistor could become forward-biased, and start to conduct and amplify its own currents, with the Drain acting as Emitter, with the N-doped well acting as Base, and with the Substrate acting as Collector. The same thing could theoretically also happen, with the P-doped Source acting as Emitter instead.

The way this behaviour was prevented, was by connecting the N-doped well to the positive supply voltage, and always keeping the P-doped substrate connected to the negative supply voltage. This formed a so-called ‘isolation diode’, and prevented the parasitical transistor from becoming active.

Well in the circuit which I had clicked together using the NG-SPICE software, each MOSFET was a 4-pin component, and my main point of attention was on how to get my software to acknowledge whatever circuits I had entered. If the circuit in question needed to be etched, using the original technology, then the bulk electrode of each MOSFET would also need to be connected either to the negative supply voltage in the case of an N-channel MOSFET, or to the positive supply voltage in the case of a P-channel MOSFET. Hence, the existence of 3-pin MOSFETs was not due to whether the transistor-type was inherently so, but just due, to how certain forms of the technology were being manufactured, as consisting of a minimal number of layers. And this also forced the inclusion of the transistors as having 3 electrodes into certain schematics, just because their implementors could not implement the 4-electrode variety in certain cases – and in fact, often.

If the schematic was ever to be etched into silicon, as I drew it in my earlier posting, and as NG-SPICE was simulating it, then at the very least, a much-more recent form of Integrated Circuit would need to be used as architecture. And then one problem which would next follow would be, that this more-recent architecture also makes the transistors much smaller, such as 40 Nanometre or 10 Nanometre technology (?), which would result in individual transistors that cannot handle the amounts of current which discrete circuits require, so that the complications of driving output pins would become more pronounced.

One reason for which I did not elaborate this fact in my past posting was the realization that I’d have to link to yet-another WiKi-page in order to do so, and that WiKiPedia articles get edited from time to time. I did not know that the WiKi would keep the traditional layout of the CMOS layers a part of their article for so long.

Also, such use of isolation diodes within the chip to this day, pose a particular risk in the case of household appliances, into which the user is required to insert batteries. Some plausible risk exists, that the user could insert the battery in a reversed direction – let’s say because that user was distracted at the moment. And then, if the battery-potentials were simply applied to the chip as supply voltages, theirĀ  reversal could cause an unhealthy, high amount of current to flow, and could fry the chip. All the isolation diodes would become forward-biased.

I could well imagine that modern circuits make up for this, by putting some sort of protection circuit for such an eventuality. But whether a protection circuit against this scenario is in fact included in low-budget appliances is really up to chance, and users might not want to gamble with the health of such appliances. And so this presents yet-another good reason, always to insert batteries with the correct polarity. More could be at stake, than whether the appliance finally works or not, when its power is switched on.


 

(Update 7/21/2019, 8h00 : )

I suppose that I can add a comment, which answers the question more directly, which the subject line of the posting suggests.

If more layers can be added to the manufacturing process, then generally, more component-types can be added to a chip. But in some cases, the economics of manufacturing speak against adding more layers, especially if this is going to be done, just so that some small number of component-instances, of the added component-type, are to be added to a circuit. This could be the case if the chip was to contain 1000 NMOS and/or PMOS transistors, but if for whatever reason, it was to include 2 diodes.

Those diodes would require an extra layer of semiconductor, actually to be added to the chip. Each layer on the chip could actually translate into an additional machine required on an assembly-line.

But there isn’t only the actual chip – i.e., the single-crystal which is so famously referred to as the monolithic component. There’s also the ‘Package’. Monolithic components are connected into a package in a way that acts like a scaled-down PC board. This technology is often referred to as ‘Thick-Film Technology’. This technology allows a SOC to exist because more than one actual chip, could be included in one package.

It would be the package that gets soldered onto a PC board, and the external appearance of which some people identify as a chip – that black rectangle of plastic, with external terminals. The actual chip is a smaller rectangle with a grey, glass-like appearance, sealed invisibly inside the package.

In some cases, a small number of instances, of that component-type which is not included according to the layers of the actual chip, will just be connected into the package.

 

There’s an interesting piece of trivia, which has essentially remained true since the 1970s, but which I don’t see mentioned anywhere. There are 3 broad categories of Integrated Circuits:

  1. Thick-Film Technology,
  2. Thin-Film Technology,
  3. Monolithic Integrated Circuits.

Thick-Film Technology comes into existence, when a solution of a chemically robust nature is printed, using similar printing methods used for ink on paper. When this solution dries, it leaves a trace of metal that may look disappointing, but that conducts electricity nonetheless. For example, a line of microscopic silver-particles could remain, that looks ‘black’, but where the fact is known that silver conducts electricity well. This is all that thick-film technology consists of, and the smallest traces that can be printed, derive from technology of standard printing presses. This form of technology can be used to interconnect several components, inside a package.

Thin-Film Technology today tends to be related to LCDs. It mainly consists of the traces of substances that can be evaporated onto a surface such as a glass surface. And one example of it exists in high-res colour LCDs. Those require transistors that act as memory circuits, so that the state of individual LCD pixels can be addressed and changed sequentially. What’s important in this application is, that the actual monolithic transistors can be deposited on the surface of the LCD and connected to it properly.

Finally, Monolithic Integrated Circuits have come a long way, mainly consisting of single-crystals of silicon, but also containing other types of layers, than were first invented as part of this category of IC. The smallest detail-size that can be put onto a monolithic IC is defined by the wavelength of ultraviolet light used, in order to harden a photo-etch layer, so that layers of silicon are not just deposited, but actually made to go away again on the regions of the chip, which were not exposed to the light, and which are therefore left sensitive to the attack of hydrogen fluoride acid.


 

I can name an example of a circuit, the eventual fabrication of which could end up becoming difficult over the stated issue. It contains series-connected diode-pairs that have capacitors at their junction, so that even given small signals, they would act both as rectifiers and voltage-doublers. But, in addition to the resistors and capacitors on the chip, the main components would be NMOS and CMOS transistors. The actual diagram, for how to put a diode onto a chip, is similar to how to add a bipolar NPN-transistor, and requires an added layer:

Monoilithic-IC-Transistor-Fabrication

The reason why the number of layers cannot simply be reduced by one, compared to what’s shown above, is that if that were the supposed layout for a diode, current flowing from the Anode to the Cathode of the diode would also flow to the (more-negative) Substrate, due to a parasitic PNP-transistor that would also form.

I.e., If current was ever to flow from the Base to the Collector of the transistor shown above, which is never how a transistor is supposed to be used anyway, then current would also flow to the Substrate, due to a second parasitic transistor which also forms.

The actual diode would form between the Base and the Emitter of this transistor above, which has already been labelled to name a parasitic component, and which should not become active when the diode conducts current. In addition to the parasitic transistor, there is also a parasitic Silicon-Controlled Rectifier, which is not supposed to switch on. In order to prevent these parasitic components from turning on, the terminal which has been labelled the Collector needs to be connected to the terminal that has been labelled the Base.

Hypothetically, If the anode of this supposed diode was to become more negative than the substrate, then current would also flow to it, from the substrate. However, because it’s standard practice to connect a P-doped substrate to the negative supply voltage, it should never happen that the anode of a diode becomes more negative than that.


 

In contrast, I’d want to be able to put resistors on such a chip, and know that a resistor can be implemented as an N-doped well, which has a zigzag shape. Because CMOS chips already have N-doped wells, as part of their P-channel MOSFETs, as well as the N+ -type silicon wells that make their connection to metal Ohmic, adding resistors of this type to a CMOS chip, will not require any additional layers…


 

Coupling capacitors would represent a special problem. I’d prefer to create monolithic capacitors, between a conductive metal layer ‘on top of an oxide layer’, that corresponds to the gate of a MOSFET, and an N-doped well, ‘underneath the oxide layer’. In an earlier posting, I explained how large the area of such a capacitor would need to be. What I had not explained yet was, that a second capacitor would automatically form, between the N-doped well and the substrate. The capacitance there would be smaller generally, than what forms with the plate, because the charge-carriers in the P-doped substrate are spread out over larger distances. In fact, positive voltage on the gate-like electrode will attract the free electrons in the N-doped well, and repel the electron-holes of the substrate. But this additional ‘capacitor to ground’ is not trivial. Hence, unless every capacitor was intended as a capacitor to ground, I’d need to connect them in such a way, that the signal-source is joined with the N-doped well, and that every time, the signal source tolerates some amount of capacitance to ground. Otherwise, there couldn’t be any coupling capacitors.


 

Because this type of capacitor-pair could be difficult to model, an alternative which might be considered would be, to invent ‘a special component’, that consists of the Gate of a P-channel MOSFET on one side, that has the Source and Drain tied together on the other side, but that also has the Bulk electrode connected to a DC supply voltage. The voltage-difference between the Gate and Bulk could fine-tune what the behaviour of such a component is supposed to be.

Dirk

 

Print Friendly, PDF & Email

One thought on “An observation about the types of logic that can be etched into silicon.”

Leave a Reply

Your email address will not be published. Required fields are marked *

You may use these HTML tags and attributes: <a href="" title=""> <abbr title=""> <acronym title=""> <b> <blockquote cite=""> <cite> <code> <del datetime=""> <em> <i> <q cite=""> <strike> <strong>

 

This site uses Akismet to reduce spam. Learn how your comment data is processed.