In This earlier posting, I described how I can use the program ‘NG-SPICE’, along with its associated GUI-applications, to create and edit circuit diagrams, and then to simulate approximately how those would function if actually implemented as circuits.
‘SPICE’ stands for ‘Simulation Program, with Integrated Circuit Emphasis’. And one of the facts which I had lamented in the posting linked to above, was that it tends to produce default transistors, that correspond to transistors one would find on an IC, those having sizes of 1 micron and smaller. Therefore I faced the challenge which I believe professional IC-designers also face, which is, to make circuits small that contain many transistors, yet, to drive output-pins of the ICs in such a way, that at least, discrete components can be connected to those output-leads, without doing so collapsing the output-waveforms.
But, my hypothetical solution to this problem will be different, from the professionally-chosen solution. What I think gets done commercially, is that special output-transistors are put on the IC, that take up greater surface-area there than unit transistors do, and which are difficult to diagram in a schematic faithfully, to how schematics depict discrete-transistor circuits. My solution was to accept the legacy n-Channel, ‘2N7000′, and the legacy p-Channel, ‘BS250P’, discrete, enhancement-mode MOSFET transistors, in the spirit that bipolar-transistor solutions are to be avoided, if the main chip-technology was MOSFET, but to mark these components as being ‘special’ – even though ages ago, the discrete components would have been regarded as ‘normal’, while the IC components would have been regarded as ‘special’, I defined those discrete components within NG-SPICE, as subcircuits, which are therefore labeled with descriptors that begin with the letter ‘X…’ , as opposed to native MOSFETs, that are to be labelled with the letter ‘M…’ .
Here are the subcircuit, Netlist-definitions of these two, now-defunct transistor-types:
I understand that this was to be an exercise, at amplifying the output of a hypothetical IC, as if with discrete components that would need to be connected to the IC externally, but remember, that equivalent, low-quality MOSFETs can be incorporated into any chips which are to be manufactured, so that in the event that they are, external components would not be necessary.
I also understand that my schematic is imperfect, in that it creates voltage-level-errors, but that such errors would become irrelevant, if the output-amplifier was put inside a feedback-loop, that has high, open-loop gain, as such a feedback loop would also just correct the voltage fed in to the circuit of this posting, so that correct output-voltages nevertheless follow.
This is the schematic:
One reason for the voltage-level errors is the fact that in this schematic, ‘X1′ and ‘X3′ do not match, and that equally, ‘X2′ and ‘X4′ do not match. Even though ‘X1′ and ‘X2′ were meant to model the threshold-voltage, with which each transistor turns on, and then to apply the correct level-shifts to the gates of ‘X3′ and ‘X4′, the main problem in my design is, that ‘X1′ is of the p-Channel type, while ‘X3′ is of the n-Channel type, and vice-versa. There was never any guarantee, that the positive threshold-voltage of the n-Channel transistor, exactly mirrors the negative threshold-voltage, of the p-Channel transistor! But, unless such an amplifier is to place a load-current onto the input-terminal,
I found no simple way to avoid this situation. As it stands, the input-terminal would offer minimum load on the circuit designed in the posting linked to above, because all it drives is floating gates. All this does is add some capacitance, while the driven output-resistance of 100Ω, is a direct function of the fact that the chosen, discrete MOSFETs, were only able to handle 200mA maximally.
Interestingly enough, the direction of the level-shift between ‘X1′ and ‘X3′ is the same, as the direction in which ‘X2′ and ‘X4′ shift the voltage-levels, which means that ‘VSD(X1)’ + ‘VDS(X2)’ == ‘VGS(X3)’ + ‘VSG(X4)’, for which reason the circuit can be expected to work anyway. And, neither the Source-Drain current through ‘X1′, nor that through ‘X2′, ever reverse, over the operating range.
(Updated 06/16/2018 : )
It can be inferred from the above paragraph, that the voltage-range of the resulting circuit, is approximately the sum, of the absolutes, of the two threshold-voltages, which in this case is approximately +2.2V and -3.2V. Therefore, in order for this circuit to work, complementary enhancement-mode MOSFETs must be chosen, which do have relatively high threshold-voltages like that. The micron-sized NMOS transistor that NG-SPICE defaults to with ‘Level=8′, tends to have threshold-voltages of only about 0.7V (?) , so that if we used such here, then our voltage-range would drop to an unusable 1.5V .
Because of that, if we wanted to go further than just a thought-experiment, and actually use such a circuit, then we might also want to replace ‘R3′ and ‘R4′ with an additional input, that defines a useful neutral-voltage. To simplify my process, I have assumed that supply voltages of +15VDC and 0V are to be used, and that the useful range of voltages is just ‘somewhere in-between’. But there is really no reason to insist, that the neutral voltage corresponds to exactly 7.5V . In the earlier schematic (not the one above) , I just assumed that a neutral, symmetric input-voltage of +6VDC would be suitable, for testing purposes, but again, the asymmetric output-voltage that corresponds to a quiescent circuit, could have been any voltage between +12VDC and +3VDC .
(As of 06/15/2018 : )
And, this is the DC voltage-sweep analysis:
As can be seen, output-voltages are only possible from 4.6V to 9.9V, that correspond to local, input-voltages from 4.5V to 10.5V . This would be the case, if the limits of the discrete components are maxed out, with a supply-voltage of 15VDC.
If ‘R1′ and ‘R2′ were made higher, in relation to ‘R3′ and ‘R4′, then a wider sub-range of voltages might be attainable, but doing so might also not guarantee sufficient S-D current, to whichever transistor out of ‘X1′ and ‘X2′ is going into its least-conductive state.