A First, Complicated Project at Circuit Design with NG-SPICE

One subject which I wrote about in an earlier posting, was that software exists by the name of ‘SPICE’, which stands for “Simulation Program with Integrated Circuit Emphasis”. There are several variants of this software in existence, but the version which I am focusing on for now is the Open-Source ‘NG-SPICE’ system, which needs to be bundled with numerous other packages under Linux, really to be useful. One important package is ‘ngspice-doc’, but there is a whole suite of Linux packages referred to as ‘gEDA’.

Simply having tested a few demo-projects, is not the same thing as actually having designed a circuit, and having witnessed that project ‘work’, at least according to the simulation. Just last night, I did the latter, in order to get a better, working grasp of how to use the software, and also, some idea of the sort of error messages and problems which invariably occur on a first-time basis. What this means is that I actually designed a circuit using the ‘gEDA Schemtic Editor’, which is also known as ‘gschem’, and then ran multiple simulations of the circuit, discovering at first that it had performance issues as I had imagined it, modifying it numerous times, and ending up with a version of the circuit, which I could be satisfied with for now.

The circuit which I was designing, actually involved MOSFETs, because those are the most important components in circuit-design today, and surely enough, I did run into initial problems. One of the tasks which we must complete, when using active components in SPICE, is to define the component, which is as fundamental as the fact that we also don’t just put a resistor, but must also specify what the Value of the resistor is in Ohms. Well with active components, we must do something similar, which also goes under the GUI heading of the Value attribute for the component. Therefore, MOSFETs, be they NMOS or PMOS, also have values, and by default, those values are defined by a Model Card, from which the computer can predict such physical properties about the NMOS or the PMOS transistor, as what its gate-capacitance is, how well it conducts when switched to conductive, conversely when the gate-voltage is zero, etc., etc., etc..

But, because NG-SPICE (v26) is advanced software – though still not the latest version – it may not require that the user defined all these parameters each time he or she considers designing a circuit, because standard component specifications exist.

By default, our MOSFETs have Reference Descriptors that begin with the letter “M”, and not with the letter “Q”, which would stand for a Bipolar Transistor, but which the GUI of ‘gschem’ suggests for the user when he first clicks a MOSFET into his circuit. So we override that, by editing the RefDes into a text-string that has the letter “M” followed without spaces by a number.

What I next proceeded to do, was to put MOSFET-transistors into my circuit, which from the GUI, only had 3 pins. This is a common way in which MOSFETs are often diagrammed, and looked something like this:


Believing that I could just accept what the GUI had constructed, I next tried to simulate the circuit, and received the error, which roughly stated “Unable to find Definition of Model.” This error-message wasted much of my time trying to solve, because I had in fact created a Model Card for the transistors which I was going to use, and at first, I despaired that NG-SPICE might not be as good as paid-for software. But I soon learned that indeed, the following example is a sufficient Model Card for an arbitrary NMOS transistor, with which circuits can be designed:


Similarly, we can conjure a default PMOS transistor like so:


In actual circuit-design, we’d drop the .TXT Filename-Extension, that makes the above examples readable in a Web-browser. Not only that, but we can also use the ‘gschem’ GUI, to embed such definitions directly into the Netlist, by giving them as a ‘Model’ attribute. So what was causing this error message, in my example? The fact is that MOSFETs are 4-pin components by nature. They have a hypothetical Source, a hypothetical Drain, a Substrate Electrode, and a Gate. It’s the voltage between the Gate and the Substrate Electrode, that finally determines how conductive the MOSFET is to become. By convention, many practical MOSFET-packages tie the Substrate Electrode together with the Source lead, which also happens to make the Source different from the Drain.


By telling NG-SPICE that we’re including a ‘MOSFET_TRANSISTOR‘ in our circuit, we’re telling this program to read 4 Nodes from the Netlist, to parse what the transistor is to be connected to. But, when the GUI only provides 3 arguments, an error ensues, that garbles the attempt of NG-SPICE to parse the Netlist. That’s all. Curiously, the reverse error does not happen. If I conjure a 4-lead MOSFET-symbol from the GUI, but specify a 3-lead MOSFET (more on that below), then I obtain a well-managed error message, that tells me what the problem is.

(Updated 06/14/2018 … )

Actually, the symbols above are also different in another way. In theory, one stands for an enhancement-mode, and the other, for a depletion-mode transistor. But, because under Linux, ‘this software is divided into two departments’, effectively, this does not matter.

The GUI allows schematics to be drawn in such a way, that Netlists result, while the actual NG-SPICE software emulates what these Netlists define. It’s in the emulation of the Netlists, that the decision is also made, as to whether a component is an enhancement-mode or a depletion-mode, or a subcircuit component… ( :1 )

(Updated 06/16/2018 : )

(As of 06/13/2018 : )

And so the way the circuit next had to evolve, which I began in such an amateurish way above, was like this:


The second circuit ran fine in my ‘gSpiceUI’ simulator, even though I had all but clicked it together from the other GUI! :-)

Now, there can be issues with performance, but those are of my own doing, and are what make circuit-design a learning process. One issue which I did run in to, is that the Model-based MOSFETs that are created as above, would correspond to MOSFETs on an actual IC, which therefore only carry small amounts of current by default, not heavy loads. And so one feat which a user like me will eventually want to perform, is actually to simulate a Discrete MOSFET, that only has 3 leads, and that can handle slightly heavier loads than micron-technology transistors do. For that explicit purpose, it’s possible to define a custom transistor using a Subcircuit, and this is fully supported by NG-SPICE, v26.

Only then, the component in question has the Reference-Descriptor that begins with the letter “X”, and the Device needs to be a ‘SUBCKT_NMOS‘ (…)

Below is a Subcircuit-Definition of a Discrete n-Channel MOSFET, which was famous, and which was known as the ‘2N7000′ :


Again please note, that (1) the .TXT Filename-Extension does not belong, and that (2) the Component Definitions are case-sensitive. We had the gumption to spell the Component Definition ‘2n7000′.

But this component also ran fine on my simulator, as long as I had ‘NG-SPICE’ selected as my back-end!

So now I have a ‘differential amplifier’. This is still not an Operational Amplifier, and I suspect that one reason fw it won’t be, is the fact that when big companies design those, they actually put components onto their ICs, which I do not have in my database. So what I have here – according to simulations – is a modest differential amplifier, that happens to reject the common-mode signal-content well, that works up to 100kHz, and that matches DC input voltages very accurately.


Yay! :-)


(Update 06/16/2018 : )

If we wanted this circuit actually to work with a more-reasonable supply-voltage of 12VDC, instead of the 15VDC I chose for testing purposes, then the way to adapt it would be, to change ‘R6′ from 30000Ω to 20000Ω . That way, the voltage-ladder created between ‘R1′, ‘R6′, and ‘R3′, would still have the appropriate voltages.

If we wanted to derive a circuit that should work with a supply-voltage of 6VDC, then we’d need to remove the two p-Channel MOSFETs, that are labeled ‘M8′ and ‘M9′ above, and that are labeled ‘M5′ and ‘M6′ below. And then, doing so would also affect performance negatively. In that case, we’d also remove ‘R6′, and set ‘R1′ at 20000Ω , which in turn, would reduce the gate-voltage of ‘M1′ from +3V to +2V .

(Update 06/13/2018, 17h00 : )

I do recall out of my ancient past, that MOSFETs were never inherently fast. They tend to suffer from the combination of low on-state conductivity, with high gate-capacitance. SPICE reflects this situation.

The type of MOSFETs used today in high-speed logic have been manufactured in a special way, that reduces unwanted capacitance.

With NG-SPICE, I could try to simulate such components, just by stating a non-default gate-capacitance in the Model Card. But before I could do that, I’d need to know how small a capacitance would be appropriate, for one high-speed MOSFET. I think this highly depends on the scale of integration, with LSI and VLSI having clear advantages due to small single-gate sizes.

Historically, especially in analog circuit-design with SSI and MSI, JFETs were thought to be faster.


(Update 06/14/2018 : )

When I designed the above iteration of my amplifier, I was trying to stay ambivalent, about whether it’s to be used in open-loop configuration – in which case it’s not an operational amplifier – or as part of a feedback loop, the latter of which really requires an op-amp.

And so the circuit stayed low-gain for some time, never really achieving amplification-factors over 30db. But the advantage was, that an analog signal could still just be applied between V1 and V2, and be amplified, and result in decently low-distortion output. If a person wanted to do that however, he’d also want to remove ‘C2′ from the circuit, which makes the circuit an integrator, but an integrator that never exceeds 30db voltage-gain.

Thus, the next goal would be to try to design an op-amp, that can only be used as part of a feedback-loop, but that does keep ‘C2′, because op-amps need to be integrators. It remained a task to improve open-loop gain. The best way in which I could hope to achieve this, was to put an additional pair of input-transistors, like so:


But then, if a person wanted to apply a signal to the inputs in an open-loop configuration, he’d get a nasty surprise like so:


In other words, even though SPICE predicts that 45db voltage-gain is achievable easily, there will be considerable distortion, which a feedback-loop would take away, from what an op-amp does.

Also, the open-loop gain achieved is hypothetical, because it depends strongly on the type of MOSFET that each transistor is exactly. And as I wrote above, this has more to do with how the ICs are mass-produced, than with the actual design of the circuit. The above circuits don’t define maximum gain.

What I can predict, is that the combination of ‘C2′ and ‘R7′, where the ideal value of ‘R7′ depends on the type of NMOS transistors, defines the speed of the sheer integration, which leaves me with 15db voltage-gain at 1MHz. If a faster integrator was needed, then the logical place to achieve that, is in reducing the capacitance of ‘C2′:




For the purpose of simulating the circuit with SPICE, decreasing ‘C2′ would pose the following problem:

The micron-sized, standard, Level-8 NMOS transistors which NG-SPICE defines, needed assistance in driving low output-impedances. I was able to achieve beautiful output-curves, that collapsed immediately, when I specified any load resistor. For that purpose, I suggested a discrete MOSFET transistor which I labeled ‘X1′, and which is only expected to act as a voltage-follower. Hence, heavier loads than 2kΩ can be accommodated, just by choosing a different component as ‘X1′ .

The way this problem gets solved in the commercial design of ICs, is that the uniform transistor which repeats itself in the main circuit, gets repeated numerous times and put in parallel, just so that the pins of the IC package can drive an output-load. Thus, ‘synthetic power-transistors’ are created, that look visibly overbearing when the IC is viewed under a microscope, but without which, we couldn’t connect a driven circuit to any outputs. This detail is often omitted, in the userland description of IC schematics.

But, my choice for ‘X1′ was actually the legacy, ‘2N7000′ discrete MOSFET transistor. It has its own gate-capacitance, which will end up in parallel with ‘C2′, but in series with the output resistor, and therefore also effectively diminished, by the amplification-factor of ‘X1′.  One would multiply the output resistance by ‘KP’, to determine by what factor to divide ‘CGSO’. On the other hand, that definition specifies a ‘CGDO’ of approximately 10pF, which does not get diminished in any circuit where the drain is simply connected to a voltage-source. Therefore, by choosing a considerable value for ‘C2′, at least I kept that predictable. A different choice for ‘X1′ could make (‘C2′) appear larger. And then, to design faster op-amp ICs, we also need to know what, exactly, ‘X1′ is to consist of.

1: )

Some online forums pose the question, of how the parameters of a model-based NG-SPICE MOSFET can be altered, to ‘make’ a depletion-mode FET. The simplest answer would seem to be, to set ‘VTO’ to a negative value, for an n-channel FET, or to a positive value, for a p-channel FET.

But, other forums explain that the procedure is not so simple. The reason would be the fact, that NG-SPICE derives ‘VTO’ from other parameters belonging to the model, and does not try to set it directly. This gets combined with some default values that are core, but that are also hard-coded into the programming. What results by default, is enhancement-mode MOSFETs.

Just as it would be in their physical design, Level-8 MOSFETs would become depletion-mode, if their parameters were altered in a more-complex way.

So, if a depletion-mode MOSFET was needed, but the circuit-designer did not know how they are also constructed physically, then perhaps, the easiest way would be not to choose a Level-8 simulation, but maybe only a Level-1 or Level-2, and then to set ‘VTO’ negative for n-channel, or positive for p-channel, thereby overriding the computed results?

BTW, With actual depletion-mode MOSFETs, a reversed voltage of about 3.0V is needed, to make them non-conductive. If they defaulted to depletion-mode under NG-SPICE, my designs would fail to work completely.

(Update 06/15/2018 : )

I’m not an expert in the design of actual transistors. But I would guess that depletion-mode MOSFETs are designed differently at the physical level, from enhancement-mode MOSFETs, to make them depletion-mode.

For example, where a standard n-Channel transistor has a p-doped well, and a separated source and drain of n-doped silicon each, a depletion-mode n-Channel is likely also to have a p-doped well, but a single n-doped channel-electrode across the source and drain. That way, when the gate behind the oxide layer goes negative, a depletion zone would form opposite the position of the gate and move gradually towards it, making the conductive region within the channel-electrode narrower.

In this way, the physical design of depletion-mode MOSFETs, may in fact be more similar, to the actual design of JFETs, except for the oxide layer replacing the actual Junction…

I should add the observation that in the case of a JFET, the junction is positioned closer to the source, than it is to the drain. This will be done, so that G-D voltage will affect conductivity less than G-S voltage does. Without this feature, a JFET would not have more than unit gain. And this feature is also different, from my description above, specifying a symmetrical MOSFET.



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