Hypothetical schema for sampling maxima and minima of a continuous analog signal.

I have just examined a hypothetical application of modern IC technology. What’s already available out-of-the-box is, that for every Analog – Digital Conversion, a single value can be generated. And today’s chips allow this to happen at 100Msps, resulting in a bandwidth of 50MHz. But for some reason, the goal might be desired, that for each of these conversions, a pair of values is generated, that accurately reflect what the maximum and minimum analog value was. As a result, a hypothetical ~oscilloscope~ could display a column of pixels, with one X-coordinate, instead of just one pixel, indicating one Y-coordinate. And so, this is the first of 3 diagrams I came up with:




My assumption is, that a 100Msps A/D Conversion will follow each of the above circuit’s 2 outputs…

(Updated 5/27/2021, 10h30… )

(As of 5/26/2021, 3h50: )

Within this circuit, a sub-circuit needs to be substituted. And the main reason why is the fact, that by itself, the circuit will continue to wait for maxima and minima, even though the analog value could have continued to progress in the same direction (positively or negatively) for more than 1 sample. If the input signal’s frequency drops below 50Mhz, I’d want a ‘spoiler circuit’, to disable what this circuit does. And so, here is the sub-circuit:




Further, in order for the first circuit actually to work, it should be fed an analog derivative of the original signal, with respect to time. However, because of the difficulty of designing a true differentiator that operates accurately up to 100MHz, I came to a realization. If the derivative function is only needed over a very limited domain of frequencies, such as, from 50MHz to 100MHz, a shortcut can be taken, in the form of a phase shifter, that achieves a 90⁰ phase-advance at a centre-frequency of 75MHz:




And so, it’s partially by blowing my spare time on projects like this, that I seem to be surviving Covid-19. :-P


The A/D Converter I’d recommend, would be the (dual-channel, 10-bit, 130Msps) ‘MAX19517 DS’. But, it doesn’t get shown in any of my schematics. It also has an internal, Sample-and-Hold Circuit.

Also, I should mention that these circuits will only tolerate a voltage-range of ±0.5V. A midpoint voltage of 0.9V is recommended, so that the outputs can be fed to the mentioned A/D Converter, without requiring any active components such as level-shifters. And, as long as the voltage-range is in fact only 1.0V, what will happen is that the power-bandwidth implied by the S/H Circuit’s slew rate, 28MHz, will match the small-signal bandwidth of the same S/H Circuit, which is 21MHz. For certain applications such as oscilloscopes, this is desirable.


(Update 5/26/2021, 13h55: )


I cannot guarantee, that any of the circuits suggested in this posting will work, as I have not run them as simulations. Nor do I plan to.

I have made other postings on this Blog, in which I used the software ‘NG-Spice’ actually to run simulations. NG-Spice stands for “Next Generation, Simulation Package with Integrated Circuit Emphasis”. My reason in those postings, not to use other versions of SPICE were, that NG-Spice just happens to be open-source software, which people are allowed to use legally for free.

One fact that I learned in those earlier exercises was, that the default behaviour even of simulated MOSFETs was unsuitable, and that for a specific purpose, the length and width of the Gate’s Rectangle are best modified – i.e., the Gate region made shorter between the Source and Drain, in order to arrive at transistors, which behave similarly to how consumer-grade, performance electronics work.

At the same time, while the oxide layer of a single chip can decrease ‘VT0′, and can ‘allow lower Gate-Source voltages to turn on a depletion-mode MOSFET’, the oxide layer must also have a uniform thickness for an entire chip, and therefore, for an entire circuit. This is typically what results in today’s low-voltage chips.

The default MOSFET parameters of NG-Spice correspond more closely, to how discrete components usually behave, which means, frequency response which begins to sag above 10 MHz, and, poor gain.

What this means is also, that any real circuit that relies on some discrete components (like the ones in this posting) are likely to suffer performance penalties in the same way, in comparison to circuits, where all the transistors are monolithic.


(Update 5/27/2021, 10h30: )

Another important reason, why the above circuit should not work is, because the ‘HA5351IBZ’ sample-and-hold IC’s performance is hindered, by the fact that this S/H has an on-chip operational amplifier, and virtually all op-amps stop working well before 100MHz.

However, the circuit can be converted into a more-plausible circuit, which would only accept signal-frequencies up to 50MHz, and still sample the signal at 2 * 100Msps, such that what my circuit would accomplish is a form of anti-aliasing. In order to accomplish that, all the active components would need to be kept as they are, but the clock-speed of the ‘spoiler’ sub-circuit would need to be reduced to 100MHz, and the value of R3 in the phase-shifter would need to be increased to 4.2kΩ.





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