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*           Electronic circuit simulation file generated by gSpiceUI           *
*                         Version 1.1.00 (2015-04-29)                          *
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* Schematic : /home/dirk/Documents/Spice/dirk/T-Line-Test_1.sch

* Component Definitions
C1 Vout 0 0.1p
O1 2 0 Vout 0 myTline1
R1 1 2 100
R2 Vout 0 40
* Signal source (Vin 1 0 0)
Vin 1 0 AC 1.00

* Model Definitions
.model myTline1 LTRA(R=1.4m L=2.5n C=1p len=20)

* NG-Spice Simulation Commands
.OPTIONS NOPAGE WIDTH=56 UNITS=RADIANS
.PRINT AC VDB(Vout)
.AC DEC 100 100.00MEG 10.00G

.END