Variable-Gain Amplifier, adapted for etching into silicon.

One of the subjects which I’ve blogged about before was, The design of a variable-gain amplifier stage, that was really a variable-attenuation stage. This stage was neither suited for direct implementation with discrete components, nor on an IC. The reason for the latter detail was, that that circuit still contained coupling capacitors. Those are difficult to implement on an IC. However, I’ve done my best to do so now, in order to design a stage, which can be etched onto an IC.

My strategy for implementing a coupling capacitor was, that I’d tie the Source, Drain and Bulk electrodes of a P-channel MOSFET together on the side of the input, and use the Gate as output. However, since the N-doped well of a P-channel MOSFET also has capacitance to the substrate, I added a schematic component, that would be a ‘Semiconductor Capacitor’ according to ‘NG-SPICE‘, and the rectangular dimensions of which would just be slightly larger in each direction, than those of the MOSFET. This is meant to simulate the added, unwanted bypass-capacitor, which the preceding transistor-stage would need to be able to overpower.

This is the schematic:


These are the model-cards used:

And this was the Net-List that defines both the circuit, and one of the simulations:

Obviously, on an actual IC, the capacitor ‘C1′ would not exist either. Instead, a presumed preceding stage would have another transistor, that does what ‘MC1′ does in this stage.

The concept behind this circuit was, that ‘M1′ is a working inverting amplifier with reasonable voltage gain – in the ballpark of ~18, if there was no circuitry designed to make it attenuate a signal. Simply because the voltage-divider exists between ‘R2′ and ‘R3′ at the input, that goes down to ~9. Additionally, the fact that ‘R5′ follows ‘MC1′, brings the voltage-gain down to ~6, when the control-voltage is 3.0V. But, as ‘M3′ starts to conduct, it starts to feed the inverted signal from the coupling-capacitor back to the Gate, where the feedback competes with the current being fed by ‘R2′. The higher the gain of ‘M1′ is, the better the negation of the signal is, that results.

All outputs should have some sort of load indicated, so I added ‘R5′. In fact, I get the impression that NG-SPICE runs into difficulty simulating an output-voltage, if there is no load resistor. But in reality, the current that flows from the Source to the Drain of ‘M3′ will also see to it that any following, chained stages are biased as this stage was biased. (:1)

This circuit has a surprising, simulated behaviour, in that it will regulate the output voltage down, almost to zero, as the control voltage increases between 4.1V and 4.25V…

(Updated 7/30/2019, 10h20 … )

Continue reading Variable-Gain Amplifier, adapted for etching into silicon.

Some Trivia about Silicon Diodes

About a century ago, the first (AM) radio receivers were made using coils, capacitors, and crude components as their only active one, called ‘Crystals’ (as well as high-impedance earphones). These crystals or ‘Whiskers’ were essentially diodes, formed from whatever mismatched pairs of conductive or semi-conductive substances a person could find, such as between ‘an iron wire’ and ‘the tarnish on a penny’. And a question which I’ve been asked was, “Why can’t the technology today just use a tuned circuit, and a silicon diode as the components?”

The answer is very basic. A silicon diode needs to have a forward voltage of at least 0.5V applied to it, before it goes from a non-conductive state to a conductive state. This is based on the Gap Energy of Silicon, or, the energy required to create an electron-electron-hole pair. It can happen that large diodes conduct some small amount of current at lower voltages, but this represents a region, in which their diffusion current is almost as low as their leakage current, which is constantly flowing in the opposite direction to the diffusion current. In short, in this sub-gap voltage-region, the diode fails to change in properties, as current flows through it in both directions, and fails to act as a diode. This amount of voltage is also referred to as ‘One Diode-Drop’.

The same thing happens between the Base and the Emitter of a Bipolar Transistor. In the NPN example, the Base must be at least one diode-drop more positive, and in the PNP example, it must be at least one diode-drop more negative than the Emitter, before the transistor ‘turns on’. This can frustrate people who try to create better rectifiers, just by connecting the Collector to the Base. This way, the curve that defines the current increases more sharply, but still only, after one diode-drop of voltage. But it can help IC designers, who want to keep Parasitic Transistors from turning on, and who can sometimes connect what would be the Base, and what would be the Emitter, of such a Parasitic Transistor, together.


(Update 7/30/2019, 0h05 : )

There is a related question which people do not generally ask me, but which I needed to know the answer to myself at some point in time. When the types of semiconductor components are drawn as a 2D layout, of a 3D construction, there is not only N-doped and P-doped silicon, but also N+ -doped and P+ -doped silicon. Why?

The answer lies in the fact that when a metal with a high work-factor, which is another way to say, with high electronegativity, comes into contact with regular, N-doped silicon, the electronegativity of the metal ‘draws away’ the majority free electrons, creating a region of silicon that behaves similarly to P-doped silicon. Right there, in that region, a “Schottky Barrier Diode” forms. And a problem in semiconductor manufacturing is, that this will happen every time the same type of metal comes into contact with the N-doped silicon, even if an Ohmic contact is desired.

Therefore, a type of N-doped silicon will be used as well, which has such an excess of dopant, that by itself, it fails to act as a semiconductor anymore. But, sandwiched between the metal and the regular N-doped silicon, it serves to form a contact, which is not a diode. In fact, if a single well of N-doped silicon has nothing but a metal junction at one end, but an N+ -doped (sub-)well with a metal contact at the other end, then what results is an actual Schottky Diode component, exploiting the junction effect on the end that does not use N+ -doped silicon. That end becomes the Anode, the side to which a positive potential needs to be applied, to result in forward conduction.

What some people might hope is that, if such a diode-type and N-doped well are incorporated into the P-doped substrate directly, this could lead to a simplified way to add diodes to CMOS logic.

However, I think that the WiKiPedia article exaggerates somewhat, about the degree by which the Schottky Diode has a lower voltage-drop, than a so-called ‘regular’ diode – a P-N diode. The diode-type which they mention: ‘1N5817′, according to my own data-sheets, only goes as low as 0.32V, at a temperature of 25⁰C. The target which the WiKiPedia suggests, of 0.15V, is only achieved at a temperature of 125⁰C. And that is pretty much the lowest-voltage of the Schottky Diodes. The voltage-drop is less than that for regular, P-N diodes, but at best, still half that.


Actually, the subject can be described in greater detail, of what the current-voltage relationship of diodes is. This requires understanding a fact about semiconductors, which is, that semiconductors only become that, above a certain temperature. Below that temperature they are insulators, and above an even higher temperature, they become regular, Ohmic conductors. This means that the thermal agitation energy of silicon is the main cause for the formation of its electron-electron-hole pairs.

Basically, a Schottky Diode is really just another diode, with a different set of parameters. The following article explains an approximation for computing the current that flows through a Schottky Diode:

This article explains the approximation for diodes in general:

Close inspection reveals that they are the same equation, essentially. This equation is also known as the “Schockley Diode Equation”. What it states in English is, that there is a constant amount of saturation current (IS), which is offset by an amount of diffusion current that is the antilogarithm of voltage. The fact that the saturation current is always flowing at a constant rate, and opposite the intended polarity, has been factorized out as the ( -1) of the term that follows (IS) both times. What this really means is that the zero-voltage (equilibrium) -current, as well as positive net currents, all exist somewhere as multiples of the same saturation current.

But there is also the Ideality Factor (N), of which the lowest numbers are most ideal, and which modulates how rapidly this antilogarithmic current changes as a function of voltage. I don’t think that (N) can become lower than (1.0).

Schottky Diodes are simply diodes, with another set of parameters. Their current curve is really continuous, just like that of regular, P-N diodes. But, they have an Ideality Factor close to (1.0), while, maybe, P-N diodes have closer to (2.0)?


Now, If one wanted to relate this equation to the Collector Current of a Bipolar Transistor, then one could say, that the resulting current has simply been multiplied by the transistor’s Current Gain…


Now, I have seen some semiconductor layouts, in which both N+ and P+ -doped silicon regions are used. But the question that I have about this is:

‘Presumably, only one type of metal coming into direct contact with the silicon is being used to make one type of IC. That type of metal can either be more electronegative or less electronegative than silicon. Therefore, it should only be necessary to use either N+ or P+ -doped silicon in the same IC, not both.’

And I have yet to see a good reply to that.