One of the facts which I’ve been writing about, is that I possess the open-source version of ‘SPICE’, that is named ‘NG-SPICE’, and that this acronym stands for ‘Simulation Program, with Integrated Circuit Emphasis’. The full, associated suite of programs allows me to edit schematic diagrams graphically, but to export ‘Netlists’, so that I can then simulate the circuit – and see if it works.
And one of the facts which I have also been contemplating, is that by default, SPICE will put transistors, which correspond to micron-sized transistors, which will therefore never be able to drive output-loads, from a hypothetical IC, unless an explicit attempt is made, to design output-buffers, which can. These output-amplifiers have as function, that they should merely follow their input voltage, but draw as little current from their respective inputs as possible – that are outputs of other, more interesting ICs – while allowing low load-resistances to be connected to their own outputs, which correspond to plausible external components, such as 100Ω load-resistors.
I had posted an earlier, conceivable design, of such an output-buffer, which had a major flaw, that I also pointed out in the preceding posting: That amplifier could only produce a range of voltages, which was a direct function of what the Gate-Source threshold voltages would be, of the component transistors used. Hence, because I had also specified low-quality, outdated MOSFET transistors with high threshold-voltages, the output-voltage-range, was also modest but reasonable. But, newer transistors will have lower threshold voltages by design, which would, oddly enough, reduce the voltage-range of that amplifier. This would be an important consideration if the transistors were not in fact discrete, but needed to be incorporated onto the IC, where low-threshold-voltage transistors are already standard. Which means, that I needed to design a better output-buffer.
So below is a better output-buffer, schematic:
And these are the SPICE definitions, of the discrete transistors which I decided to base my design on again, both enhancement-mode MOSFETs:
The main disadvantage of this latest design would be, that the transistors which I labeled ‘X2′ and ‘X3′, do in fact conduct current to their combined inputs, which makes the additional transistor ‘X1′ necessary, since this amount of current would already be excessive, to connect to an output, of any pre-existing IC circuits. But then, the advantage goes so far, that ‘X2′ now models a level-shift, which exactly mirrors the level-shift of ‘X4′, and the voltage-level-shift of ‘X3′ now mirrors ‘X5′. There is design beauty in this. But one disadvantage now is, that the Gate-Source threshold-voltage of (1) n-Channel MOSFET (2.2V) plus (1) p-Channel MOSFET (3.2V) gets subtracted from the input-voltage, so that the available voltage-range still suffers, with respect to both the supply, and the input-voltage. Input-voltage now ranges from 5.4V to approximately 12.5V, which is closer to the range of supply-voltages than what the previous circuit allowed, and the resulting output-voltages are graphed below:
There is another observation which I should add:
The 2N7000, enhancement-effect, n-Channel MOSFET – again, an outdated transistor – has as its own Gate-Source capacitance, 180nF. If we multiply the transconductance of this transistor with the pull-down resistor’s value, we obtain the factor by which this transistor’s Gate-Source voltage changes less, than its mere Gate voltage with respect to Common. The apparent capacitance at the input gets reduced, because the current drawn by the real Gate-Source capacitance, will still be proportional to Gate-Source voltage-changes, when the circuit is active: In this case, reduced by a factor of 200. Therefore, the use of such a transistor will still cause ~1nF of input-capacitance to appear. This could be important, if the local input is also connected directly to the active circuit, perhaps a fast integrator, already defined by the preceding output-capacitance. In one earlier design, I suggested that 150pF should be used. But, because those 150pF would now be in parallel with a virtual, 1nF input-capacitance, the ideal of 150pF will never happen – Unless, we use better transistors.
(Updated 06/18/2018, 14h55 … )
The low-end output-voltage comes into being as follows: