One of the subjects which I’ve blogged about before was, The design of a variable-gain amplifier stage, that was really a variable-attenuation stage. This stage was neither suited for direct implementation with discrete components, nor on an IC. The reason for the latter detail was, that that circuit still contained coupling capacitors. Those are difficult to implement on an IC. However, I’ve done my best to do so now, in order to design a stage, which can be etched onto an IC.
My strategy for implementing a coupling capacitor was, that I’d tie the Source, Drain and Bulk electrodes of a P-channel MOSFET together on the side of the input, and use the Gate as output. However, since the N-doped well of a P-channel MOSFET also has capacitance to the substrate, I added a schematic component, that would be a ‘Semiconductor Capacitor’ according to ‘NG-SPICE‘, and the rectangular dimensions of which would just be slightly larger in each direction, than those of the MOSFET. This is meant to simulate the added, unwanted bypass-capacitor, which the preceding transistor-stage would need to be able to overpower.
This is the schematic:
These are the model-cards used:
And this was the Net-List that defines both the circuit, and one of the simulations:
Obviously, on an actual IC, the capacitor ‘C1′ would not exist either. Instead, a presumed preceding stage would have another transistor, that does what ‘MC1′ does in this stage.
The concept behind this circuit was, that ‘M1′ is a working inverting amplifier with reasonable voltage gain – in the ballpark of ~18, if there was no circuitry designed to make it attenuate a signal. Simply because the voltage-divider exists between ‘R2′ and ‘R3′ at the input, that goes down to ~9. Additionally, the fact that ‘R5′ follows ‘MC1′, brings the voltage-gain down to ~6, when the control-voltage is 3.0V. But, as ‘M3′ starts to conduct, it starts to feed the inverted signal from the coupling-capacitor back to the Gate, where the feedback competes with the current being fed by ‘R2′. The higher the gain of ‘M1′ is, the better the negation of the signal is, that results.
All outputs should have some sort of load indicated, so I added ‘R5′. In fact, I get the impression that NG-SPICE runs into difficulty simulating an output-voltage, if there is no load resistor. But in reality, the current that flows from the Source to the Drain of ‘M3′ will also see to it that any following, chained stages are biased as this stage was biased. (:1)
This circuit has a surprising, simulated behaviour, in that it will regulate the output voltage down, almost to zero, as the control voltage increases between 4.1V and 4.25V…
(Updated 7/22/2019, 15h30 … )