## Variable-gain amplifier, with good frequency response including 4MHz.

In an earlier posting, I had described a variable-gain amplifier that could be etched into a monolithic IC. But, that circuit had as its main drawback, that it would only seem to work well at a centre-frequency of ~500kHz, while most circuit designs expect Megahertz frequencies, when working in the analog domain.

The diagrams in this posting have been tested using the open-source simulation software named ‘NG-Spice’.

In order to achieve Megahertz frequency response, I needed to discover a little trick, which professional circuit designers – aka Electrical Engineers – probably already know. What the previous circuit had done, was to set (R4) to 32kΩ, while setting (R1) to 40kΩ. The reason I had done this was, the old-fashioned idea that the pull-up resistor of the amp should bisect the supply voltage, with the main transistor in series, in order to achieve maximum gain. Yet, the bias voltages were more likely to be in the vicinity of 1.8V. Thus, (R4) would bias (M2) to conduct a certain amount of current, and because both (M1) and (M4) are in saturation mode, they will both conduct the same amount of bias current between their Source and Drain, due to the resulting bias voltage at both Gates. Yet, that amount of current would cause a 1.5V voltage-drop through (R1), while causing a 1.2V voltage-drop through (R4).

Hence, with 2 voltage-levels, it was necessary to put a coupling capacitor, which in turn is a hassle on an IC.

The trick seems to be, that (R1) and (R4) can be set to the same value, so that the DC component of the Drain voltage, will equal the bias voltage. That way, as many circuits as needed can just be chained, with equal bias voltages, and No Coupling Capacitors. The bias voltage I now obtain, is (1.857V).

Additionally, I retuned the circuit, by reducing the width of (M1) and (M2) from 100μM to 25μM, which in turn reduces Drain-to-Gate capacitance, which in turn would hinder good, high-frequency response. (M4) now also has a width of 25μM, so that it can be biased in a matching way.

Yet, with the transistors so small, the output would need to be protected by that additional transistor (M4), so that to connect minor loads to it will not collapse the functioning of the main stage.

The result was, that with a control voltage of (2.0V) and a frequency of 4MHz, a gain of almost +40dB was obtained, while with a control voltage of (0.0V), a signal drop, and indeed inversion of the phase was obtained, because (M3) just bypassed (M1).

The following is the Netlist of the (2.0V) simulation:

http://dirkmittler.homeip.net/text/Default_NM_Gain_IF_13.net.txt

And these are the Modelcards of the transistors used:

http://dirkmittler.homeip.net/text/NMOS2.mod.txt

http://dirkmittler.homeip.net/text/PMOS2.mod.txt

This is an image of the schematic:

(Updated 5/29/2021, 12h15… )

## Basic Colpitts Oscillator

One of the concepts which I’ve been exploring on my blog, concerns tuned circuits, and another concerns Voltage-Controlled Oscillators (VCOs). As one type of voltage-controlled oscillator, I have considered an Astable Multivibrator, which has as advantage a wide frequency-range, but which will eventually have as disadvantage, a limited maximum frequency, when the supply voltage is only 3V. There could be other more-complex types of VCOs that apply, when, say, 200MHz is needed, but one basic type of oscillator which will continue to work under such conditions, which has been known for a century, and which will require an actual Inductor – a discrete coil – is called the Colpitts Oscillator. Here is its basic design:

In this schematic I’ve left out actual component values because those will depend on the actual frequency, the available supply voltage, on whether a discrete transistor is to be used or an Integrated Circuit, on whether a bipolar transistor is to be used or a MOSFET… But there are nevertheless certain constraints on the component-values which apply. It’s assumed that C1 and C2 form part of the resonant “Tank Circuit” with L1, that in series, they define the frequency, and that they are to be made equal. C3 is not a capacitor with a critical value, instead to be chosen large enough, just to act as a coupling-capacitor at the chosen frequency (:2) . R2 is to be made consistent with the amount of bias current to flow through Q1, and R1 is chosen so that, as labelled, the correct bias voltage can be applied, in this case, to a MOSFET, without interfering with the signal-frequency, supplied through C3.

I’m also making the assumption that everything to the right of the dotted line would be put on a chip, while everything to the left of the dotted line would be supplied as external, discrete components. This is also why C3, a coupling capacitor, becomes possible.

The basic premise of this oscillator is that C1 and C2 do not only act as a voltage-divider, but that, when the circuit that forms between L1, C1 and C2 is resonant with a considerable Q-factor (>= 5), C1 and C2 actually act as though they were a centre-tapped auto-transformer. If this circuit was not resonating, the behaviour of C1 and C2 would not be so. But as long as it is, it’s possible for a driving voltage, together with a driving current, to be supplied to the connection between C1 and C2, in this case by the Source of Q1, and that the voltage which will form where C1 connects with both L1 and the Gate of Q1 (that last part, through C3), will essentially be the former, driving voltage doubled. Therefore, all that needs to happen on the part of the active component, is to form a voltage-follower, between its Gate and Source, so that the voltage-deviations at the Source, follow from those at the Gate, with a gain greater than (0.5). If that can be achieved, the open-loop gain of this circuit will exceed (1.0), and it will resonate.

It goes without say that C1 and C2 will also isolate whatever DC voltage may exist at the Source of Q1, from the DC voltage of L1.

There is a refinement to be incorporated, specifically to achieve a VCO. Some type of varactor needs to be connected in parallel with L1, so that low-frequency voltage-changes on the varactor will change the frequency at which this circuit oscillates, because by definition, a varactor adds variable capacitance.

What some sources will suggest is that, the best way to add a varactor to this circuit will be, to put yet-another coupling capacitor, and a resistor, the latter of which supplies the low-frequency voltage to the varactor. But I would urge my reader to be more-creative, in how a varactor could be added. One way I could think of might be, to get rid of R1 and C3, and instead of terminating L1 together with C2 to ground, to terminate them to the supply voltage, thus ensuring that Q1 is biased ‘On’, even though the coupling capacitor C3 would have been removed in that scenario. What would be the advantage in this case? The fact that The varactor could be implemented on-chip, and not supplied as yet-another, external, discrete component, many of which would eat up progressively more space on a circuit-board, as a complex circuit is being created.

I should also add that some problems will result, if the capacitance to be connected in parallel with L1 becomes as large, as either C1 or C2. An eventual situation will result, in which C1 and C2 stop acting, as though they formed a (voltage-boosting) auto-transformer. An additional voltage-divider would form, between C1 in this case, and the added, parallel capacitance. And this gives more food for thought. (:1)

(Possible Usage Scenario : )

(Updated 7/29/2019, 14h45 … )

## Variable-Gain Amplifier, adapted for etching into silicon.

One of the subjects which I’ve blogged about before was, The design of a variable-gain amplifier stage, that was really a variable-attenuation stage. This stage was neither suited for direct implementation with discrete components, nor on an IC. The reason for the latter detail was, that that circuit still contained coupling capacitors. Those are difficult to implement on an IC. However, I’ve done my best to do so now, in order to design a stage, which can be etched onto an IC.

My strategy for implementing a coupling capacitor was, that I’d tie the Source, Drain and Bulk electrodes of a P-channel MOSFET together on the side of the input, and use the Gate as output. However, since the N-doped well of a P-channel MOSFET also has capacitance to the substrate, I added a schematic component, that would be a ‘Semiconductor Capacitor’ according to ‘NG-SPICE‘, and the rectangular dimensions of which would just be slightly larger in each direction, than those of the MOSFET. This is meant to simulate the added, unwanted bypass-capacitor, which the preceding transistor-stage would need to be able to overpower.

This is the schematic:

These are the model-cards used:

http://dirkmittler.homeip.net/text/NMOS2.mod.txt

http://dirkmittler.homeip.net/text/PMOS2.mod.txt

http://dirkmittler.homeip.net/text/JUNCCAP1.mod.txt

And this was the Net-List that defines both the circuit, and one of the simulations:

http://dirkmittler.homeip.net/text/Default_NM_Gain_IF_6.net.txt

Obviously, on an actual IC, the capacitor ‘C1′ would not exist either. Instead, a presumed preceding stage would have another transistor, that does what ‘MC1′ does in this stage.

The concept behind this circuit was, that ‘M1′ is a working inverting amplifier with reasonable voltage gain – in the ballpark of ~18, if there was no circuitry designed to make it attenuate a signal. Simply because the voltage-divider exists between ‘R2′ and ‘R3′ at the input, that goes down to ~9. Additionally, the fact that ‘R5′ follows ‘MC1′, brings the voltage-gain down to ~6, when the control-voltage is 3.0V. But, as ‘M3′ starts to conduct, it starts to feed the inverted signal from the coupling-capacitor back to the Gate, where the feedback competes with the current being fed by ‘R2′. The higher the gain of ‘M1′ is, the better the negation of the signal is, that results.

All outputs should have some sort of load indicated, so I added ‘R5′. In fact, I get the impression that NG-SPICE runs into difficulty simulating an output-voltage, if there is no load resistor. But in reality, the current that flows from the Source to the Drain of ‘M3′ will also see to it that any following, chained stages are biased as this stage was biased. (:1)

This circuit has a surprising, simulated behaviour, in that it will regulate the output voltage down, almost to zero, as the control voltage increases between 4.1V and 4.25V…

(Updated 5/28/2021, 23h45 … )