Playing with NG-SPICE again, and designing two resonant-circuit bandpass filters.

NG-SPICE is a program designed to simulate circuits. The acronym stands for (Next Generation) Simulation Program, with Integrated Circuit Emphasis. While NG-SPICE is open-source, its cousins such as LT-SPICE and PSpice are proprietary. However, NG-SPICE also uses advanced Mathematical modelling of components and circuits. Sometimes I find it to be an educational toy.

A type of circuit which some people might find interesting, is the IF strip – the Intermediate Frequency stage – of a radio receiver, which receives its signal after the Radio-Frequency signal has been ‘mixed’ with a Local Oscillator, and heterodyned down to the Intermediate Frequencies. And due to modern technology, a final, intermediate frequency of 450kHz can be used both for AM and FM demodulation.

There is a type of resonant circuit that employs capacitors and inductors – i.e., coils, in order to accomplish two things:

• To act as a bandpass filter, restricting the frequency range,
• To establish a phase-shift between the incoming carrier wave, and an oscillating, derived wave, that is dependent on the momentary frequency of the carrier wave, so that later in the analog processing of the signal, a phase-discriminator can complete the task of FM demodulation. This task is also referred to as Quadrature Demodulation of an FM carrier.

This type of resonant circuit is also sometimes referred to as a “Tank Circuit”.

In short, I’ve been reinventing the wheel. But I did read an article from elsewhere on the Internet, which inspired me. The subject of that article was, how to design Varactors, which are variable-capacitance diodes, when restricted to only using CMOS transistor-pairs. These diodes would represent a good way to tune circuits and vary the frequency of oscillators, in many types of applications. But I had an application in mind, which this type of varactor would help me solve. The mentioned, “IMOS Varactors” are remarkable because they don’t actually involve any diodes. They involve a way to connect an enhancement-mode P-channel MOSFET, so that the effect of gate-voltage changes on the MOSFET’s gate capacitance, acts as a varactor.

If somebody is designing a tuned circuit using the smallest, most-modern coils, manufactured by high-tech factories, then those coils allow for a high Q-factor to exist, which is a measure of how selective the filter can become, as well as to have good thermal stability, but if they are on a budget, these components will have some amount of tolerance, meaning that in a constant way, each component’s actual inductance value will vary to some degree. This is especially unfortunate since high-quality inductors on a budget, are also unlikely to be tunable. If the inductor in question is of a better sort, that ‘only’ has 5% tolerance, this would mean that with an improperly designed radio tuned to an intended AM frequency of 800kHz, instead, the listener could end up receiving a station at 780kHz, or at 820kHz, just because this one filter’s frequency is off by 5%. Of course, real radios that are designed to any level of satisfaction don’t behave that way.

What can be done, is that in the assembly-process for the radio, some machine calibrates its tuned circuits. But again, a maximal use of the main integrated circuit is assumed, and a minimal expense of external, discrete components is assumed. Here, a trimming potentiometer is a more-affordable way to do, what back in the 1970s and 1980s, tunable inductors would have done. If the assumption was made that for reasons I won’t go in to here, The IC can hold an exact voltage steady, then this voltage can also be applied to varactors internal to the IC, in a way that corrects for whatever amount of error was present in the coil.

Even though today, tunable inductors can be bought in quantity that also offer a Q-factor of 48, those aren’t just more expensive than the fixed variety. In addition, those would be much larger components, measuring maybe ‘half a centimetre’ cubed, and requiring to be soldered in to the circuit-board, while the fixed sort can be much smaller units, soldered onto a circuit-board as a surface-mounted device.

And so, reinventing the wheel in order to educate myself, what I have done was to design two circuits, one of which tunes in to 450kHz with the aid of such monolithic varactors, and the second of which does the same at 10Mhz instead. I’m using transistors that are not the tiniest in existence, but which are still too tiny, for an implementation of these ideas to be attempted with discrete components. Capacitances in picofarads should act as a warning to any reader, not to try this with discrete components. It’s much less-risky financially, just to run some simulations using NG-SPICE…

(Updated 7/27/2019, 12h05 … )

NG-SPICE: Biasing the Default Transistor for Ideal Linear Voltage Gain, at 3V.

In recent days and weeks, I’ve been studying some of my own ideas, concerning the creative uses of the N-Channel, Enhancement-Mode, MOSFET. And to help me explore that subject, I’ve used An Open-Source Circuit Simulation Program called ‘NG-SPICE’. One big problem with this approach is the fact that the default transistor that the software assumes the power-user wants to use, is clearly not meant for Linear Voltage Amplification in the 100kHz-1.0Mhz frequency range, and with a 3V supply voltage. This transistor type is meant to be operated at higher voltages, and mainly, for digital uses. All the software is geared for Integrated Circuit Emphasis. But, I have looked at possible ways in which the default transistor could still be used under the conditions I’m more interested in. In theory, I could change the parameters of the transistor involved as much as I like, until I’ve made a high-speed, low-voltage transistor out of it. One problem with that is the fact that I give the software the geometry of the transistor on a chip, and the software then derives many of its assumed properties. I don’t know much about IC design, so I probably would not obtain the kind of transistor I’m looking for, if I tried to invent one.

So the question comes back, what is the best way to bias this one, arbitrary transistor-type, to act as a high-impedance amplifier under the conditions written above? And how much gain does it give me? The answer seems to be, that when connected as below, the best performance I can obtain is an Alpha of (-5.25):

What I’ve also learned is, that the bias voltage associated with this circuit, with respect to ground, is (+2.14V). With respect to the supply voltage, that is (-0.86V). 3.75μV of bias current would need to flow. This information would be useful if an attempt ever came along to implement This Idea.

(Edit 7/5/2019, 17h15 : )

Doubling (VGS – VT0) of M1 would have as effect, that IDS quadruples. It would also have as effect, that equal, small changes in Gate Voltage translate into doubled changes in IDS. But, if the increase in bias current was taken into account by the circuit designer, by putting a resistor of merely 100kΩ in series with M1, thereby achieving that the supply voltage was ideally halved again as a result, then this would finally have as effect to halve the net voltage gain at the Drain of M1.

It would also have as effect, to quarter output impedance, which would be desirable from the last of a series of these stages, ending in a realistic load of some kind.

(End of Edit, 7/5/2019, 17h15.)

The Model-Card of the transistor is linked below:

http://dirkmittler.homeip.net/text/NMOS1.mod.txt

To pursue the exact subject of the earlier posting, about Variable-Gain Amplifiers, I also felt that it would be necessary to add to the circuit the components, that would transform it into a variable attenuator. And the following schematic shows how I did that:

(Updated 7/16/2019, 7h50 … )

An observation about the types of logic that can be etched into silicon.

One of the questions which I had blogged about before, was that, of whether the MOSFET transistor-type inherently has 3 pins or 4. This question has a practical aspect, which I did not mention in that posting, but which is eventually interesting.

When the very high-end Electrical Engineers design chips – ICs – and specifically, when they designed earlier-generation CMOS circuitry, they were not only limited by what the fundamental properties of a MOSFET were, but also, by how many layers the machines at the time could deposit onto the chip, each of which needed to be etched and treated in a separate, very precise stage of the manufacturing process. This is why I find it helpful that the WiKiPedia article I just linked to, displays a CMOS circuit, and how it was originally implemented, as their explanation of the subject.

What the reader may take note of, is the example of the P-channel MOSFET, which consists of a Source, a Drain, a Gate, a Bulk Electrode, and a Substrate. The role of this Bulk Electrode needs to be given some special attention. Because of the way these transistors were in fact etched, additional, unintentional, “parasitical” transistors could form, for example, a ‘hidden’ PNP, Bipolar Transistor, between the Drain, the N-doped well, and the P-doped substrate. In theory, if the N-doped well became negative enough, with respect to either the potential of the substrate or that of the P-doped Drain, then this parasitical transistor could become forward-biased, and start to conduct and amplify its own currents, with the Drain acting as Emitter, with the N-doped well acting as Base, and with the Substrate acting as Collector. The same thing could theoretically also happen, with the P-doped Source acting as Emitter instead.

The way this behaviour was prevented, was by connecting the N-doped well to the positive supply voltage, and always keeping the P-doped substrate connected to the negative supply voltage. This formed a so-called ‘isolation diode’, and prevented the parasitical transistor from becoming active.

Well in the circuit which I had clicked together using the NG-SPICE software, each MOSFET was a 4-pin component, and my main point of attention was on how to get my software to acknowledge whatever circuits I had entered. If the circuit in question needed to be etched, using the original technology, then the bulk electrode of each MOSFET would also need to be connected either to the negative supply voltage in the case of an N-channel MOSFET, or to the positive supply voltage in the case of a P-channel MOSFET. Hence, the existence of 3-pin MOSFETs was not due to whether the transistor-type was inherently so, but just due, to how certain forms of the technology were being manufactured, as consisting of a minimal number of layers. And this also forced the inclusion of the transistors as having 3 electrodes into certain schematics, just because their implementors could not implement the 4-electrode variety in certain cases – and in fact, often.

If the schematic was ever to be etched into silicon, as I drew it in my earlier posting, and as NG-SPICE was simulating it, then at the very least, a much-more recent form of Integrated Circuit would need to be used as architecture. And then one problem which would next follow would be, that this more-recent architecture also makes the transistors much smaller, such as 40 Nanometre or 10 Nanometre technology (?), which would result in individual transistors that cannot handle the amounts of current which discrete circuits require, so that the complications of driving output pins would become more pronounced.

One reason for which I did not elaborate this fact in my past posting was the realization that I’d have to link to yet-another WiKi-page in order to do so, and that WiKiPedia articles get edited from time to time. I did not know that the WiKi would keep the traditional layout of the CMOS layers a part of their article for so long.