Variable-Gain Amplifier, adapted for etching into silicon.

One of the subjects which I’ve blogged about before was, The design of a variable-gain amplifier stage, that was really a variable-attenuation stage. This stage was neither suited for direct implementation with discrete components, nor on an IC. The reason for the latter detail was, that that circuit still contained coupling capacitors. Those are difficult to implement on an IC. However, I’ve done my best to do so now, in order to design a stage, which can be etched onto an IC.

My strategy for implementing a coupling capacitor was, that I’d tie the Source, Drain and Bulk electrodes of a P-channel MOSFET together on the side of the input, and use the Gate as output. However, since the N-doped well of a P-channel MOSFET also has capacitance to the substrate, I added a schematic component, that would be a ‘Semiconductor Capacitor’ according to ‘NG-SPICE‘, and the rectangular dimensions of which would just be slightly larger in each direction, than those of the MOSFET. This is meant to simulate the added, unwanted bypass-capacitor, which the preceding transistor-stage would need to be able to overpower.

This is the schematic:

Default_NM_Gain_IF_6

These are the model-cards used:

http://dirkmittler.homeip.net/text/NMOS2.mod.txt

http://dirkmittler.homeip.net/text/PMOS2.mod.txt

http://dirkmittler.homeip.net/text/JUNCCAP1.mod.txt

And this was the Net-List that defines both the circuit, and one of the simulations:

http://dirkmittler.homeip.net/text/Default_NM_Gain_IF_6.net.txt

Obviously, on an actual IC, the capacitor ‘C1′ would not exist either. Instead, a presumed preceding stage would have another transistor, that does what ‘MC1′ does in this stage.

The concept behind this circuit was, that ‘M1′ is a working inverting amplifier with reasonable voltage gain – in the ballpark of ~18, if there was no circuitry designed to make it attenuate a signal. Simply because the voltage-divider exists between ‘R2′ and ‘R3′ at the input, that goes down to ~9. Additionally, the fact that ‘R5′ follows ‘MC1′, brings the voltage-gain down to ~6, when the control-voltage is 3.0V. But, as ‘M3′ starts to conduct, it starts to feed the inverted signal from the coupling-capacitor back to the Gate, where the feedback competes with the current being fed by ‘R2′. The higher the gain of ‘M1′ is, the better the negation of the signal is, that results.

All outputs should have some sort of load indicated, so I added ‘R5′. In fact, I get the impression that NG-SPICE runs into difficulty simulating an output-voltage, if there is no load resistor. But in reality, the current that flows from the Source to the Drain of ‘M3′ will also see to it that any following, chained stages are biased as this stage was biased. (:1)

This circuit has a surprising, simulated behaviour, in that it will regulate the output voltage down, almost to zero, as the control voltage increases between 4.1V and 4.25V…

(Updated 7/30/2019, 10h20 … )

(As of 7/21/2019, 20h15 : )

Screenshot_20190721_194300

Screenshot_20190721_201133

Hence, this circuit works very well.


I seem to have stumbled upon a behaviour of MOSFETs that is new to me. If there is a high, positive potential between both the Source and the Drain on one side, of an enhancement-mode, N-channel MOSFET, and its Bulk on the other side, then the Gate voltage required to make it conduct increases dramatically. 4.1V is more than twice 1.8V, which is usually enough to make ‘M1′, or ‘M2′, start conducting well.

I suppose that an important question to ask next would be, ‘Where does a circuit derive a voltage up to 4.1V, in order to make such an attenuator work, if the supply voltage is only 3V?’ But I can think of answers to that question.

This is quite different, from the hypothetical circuit this idea started as, which could be constructed from discrete capacitors, and which might work, on a trial-and-error basis.


 

(Update 7/22/2019, 15h30 : )

1:)

The circuit-simulator may have as a peculiarity, that some quantity of resistance needs to be connected to the output, just so that the Source-Drain resistance of ‘M3′ will be added in parallel with it. This would be similar behaviour, to what I already encountered, when simulating a tuned, resonant circuit. There, in the 450kHz example, I needed to connect explicit 10pF capacitors where the Gates of the MOSFETs were, the latter acting as variable capacitors. Failing to connect explicit capacitors there, resulted in a simulation that did not work, even though the capacitance at those Gates should have been enough to make the circuit work. In a practical circuit, one would just rely on the Gate-capacitance to make the circuit work.

But there is more insight to gain, about the role which ‘R5′ plays in this circuit. I had written that it reduces gain. But it may do so for reasons aside, from the fact that it puts another load on the capacitance implied by ‘MC1′. ‘R5′ also adds negative feedback. The reason for that lies in the practice of using one extra transistor, in this case ‘M2′, just to calculate how much bias-voltage to apply to the Gate of ‘M1′, when each time, the Source and Bulk are connected – in this case, ‘Bulk’ and ‘Substrate’ mean the same thing – so that ‘M1′ will conduct the required amount of bias current, in saturation mode.

The voltage which ‘M2′ is determining, is not a strongly buffered voltage. When there is an additional stage using ‘M2′ to determine its bias, even if that stage is configured identically to the stage shown, current that will flow through ‘R5′ in this case, will have some positive effect on the voltage at the Gate of ‘M2′. Because that voltage is also determining the bias of ‘M1′, feedback can result. In this case I’m lucky because the resulting feedback is negative feedback, and that just happened to be what I already needed. But generally, if multiple stages are being connected into a sequence, that type of feedback can act against the way the circuit has been designed. And if the net effect of such stages is a high amount of voltage gain, then additional bias-determining transistors, such as ‘M2′, need to be included on the IC, even when all the stages in question are to be configured the same way.

 

(Update 7/30/2019, 10h20 : )

I’ve looked in to the subject, of whether merely to increase the channel-length of ‘M3′, resolves the problem, of high positive control-voltages required, to regulate the attenuation. And it does not. A longer channel-length will merely have as effect, a more-gradual transition, between minimum and maximum attenuation. And the behaviour makes sense in retrospect.

It’s an N-channel, enhancement-mode MOSFET. Because both the N-doped Source and Drain are highly positive with respect to the P-doped Substrate, each is reverse-biased, and surrounded by a large depletion region. The (positive) Gate voltage must first negate that depletion region, and then exceed that requirement by adding the threshold voltage, before the transistor can become conductive. Putting more distance between Source and Drain won’t change that. And NG-SPICE was programmed well-enough to take this effect into account, when doing a Level-8 simulation.

If the goal was to design a 3V-powered radio with this circuit, then the signal which must be controlled, after all the amplification-circuits, could be fed into a system of 4 Schottky Diodes and 4 capacitors, that act as a voltage-quadrupler. This set of Schottky Diodes would be connected to the positive supply voltage, and would reduce the zero-signal, low-frequency output by 1.4 Volts already, just because of the 4 diodes in series. But then, starting with 1.6V, it needs to achieve ~4V, meaning that the peak amplitude of the signal will be a controlled 0.6V.

Alternatively, the downstream signal could be fed to a voltage doubler, the effect of which would be to drop the zero-signal control-voltage to +2.3V due to two Schottky Diodes connected in series, so that in order to be boosted to +4V, the signal being measured would need to have a peak amplitude of 0.85V. Doing this may necessitate that the signal which is being controlled be amplified, before being fed to the voltage doubler.


 

This problem may be resolved more easily, if ‘M3′ is made a P-channel MOSFET instead, with the Bulk voltage of its N-doped well, connected to the voltage already used as bias, for ‘M1′. Now, as the control voltage changes from +0.4V to 0.0V, the circuit goes from full gain to full attenuation, which will bring as benefit, that only two diodes and two capacitors would be needed, connected to the negative supply voltage and facing in the other direction. Hence, ‘only’ having a voltage-doubler is attainable theoretically.

In this case, with a signal-strength of zero, a bridge of Schottky Diodes will produce +0.7V. But then, in order to yield 0.0V, the signal as measured at a later stage of amplification would need to have an AC peak amplitude of 0.35V…

Default_NM_Gain_IF_8

 

http://dirkmittler.homeip.net/text/Default_NM_Gain_IF_8.net.txt


This particular arrangement presents the problem, that (VGS-VT0) is never very high, for which reason (VDS) must also never be very high, so that ‘M3′ will still operate in triode mode. This circuit could be placed early in an IF strip, where the signal amplitude is still quite small – i.e., less than 0.05V peak – so that the feedback-voltages from a later stage, acting as (Vcontrol) in this stage, will overpower those signal amplitudes. Yet, signal-distortion could potentially remain a problem here.

Because this circuit, unlike the previous one, does not require control-voltages that are outside the range of supply voltages, an alternative to voltage-multiplying diode ladders presents itself. For example, if again, this was to form part of an IF strip, of an AM/FM radio, then, in order to operate in AM mode, that radio could have a balanced demodulator ready, which would implement synchronous demodulation, to which end the same radio would also have a VCO running, to capture the amplitude-phase of an AM carrier. This VCO might be designed to be agile enough, to keep a lock on an FM carrier, when the radio is in FM mode.

The benefit of such circuitry, which I did not display here, could be, that on the side of the balanced demodulator which is negative to the amplitude of the carrier, a DC voltage could be tapped and a level-shift applied, as the threshold voltage of one N-channel, MOSFET (-1.8V). Carrier amplitudes strong enough to work this demodulator could send the voltage on that side down (towards zero), so that attenuation would start to happen, in the circuit which I displayed above.

Simultaneously, on the side of the balanced demodulator which is positive with the carrier amplitude, a minimum voltage could be required, to turn audio output on… And this situation could be made to correspond to a (Vcontrol) value in the circuit shown above, of (+0.3V), thereby assuring partial attenuation, and zero distortion, as a precondition. (Vcontrol) begins to have an effect, at (+0.35V).

Dirk

 

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