NG-SPICE: Biasing the Default Transistor for Ideal Linear Voltage Gain, at 3V.

In recent days and weeks, I’ve been studying some of my own ideas, concerning the creative uses of the N-Channel, Enhancement-Mode, MOSFET. And to help me explore that subject, I’ve used An Open-Source Circuit Simulation Program called ‘NG-SPICE’. One big problem with this approach is the fact that the default transistor that the software assumes the power-user wants to use, is clearly not meant for Linear Voltage Amplification in the 100kHz-1.0Mhz frequency range, and with a 3V supply voltage. This transistor type is meant to be operated at higher voltages, and mainly, for digital uses. All the software is geared for Integrated Circuit Emphasis. But, I have looked at possible ways in which the default transistor could still be used under the conditions I’m more interested in. In theory, I could change the parameters of the transistor involved as much as I like, until I’ve made a high-speed, low-voltage transistor out of it. One problem with that is the fact that I give the software the geometry of the transistor on a chip, and the software then derives many of its assumed properties. I don’t know much about IC design, so I probably would not obtain the kind of transistor I’m looking for, if I tried to invent one.

So the question comes back, what is the best way to bias this one, arbitrary transistor-type, to act as a high-impedance amplifier under the conditions written above? And how much gain does it give me? The answer seems to be, that when connected as below, the best performance I can obtain is an Alpha of (-5.25):

Default_NM_Gain_IF_1

What I’ve also learned is, that the bias voltage associated with this circuit, with respect to ground, is (+2.14V). With respect to the supply voltage, that is (-0.86V). 3.75μV of bias current would need to flow. This information would be useful if an attempt ever came along to implement This Idea.

(Edit 7/5/2019, 17h15 : )

Doubling (VGS – VT0) of M1 would have as effect, that IDS quadruples. It would also have as effect, that equal, small changes in Gate Voltage translate into doubled changes in IDS. But, if the increase in bias current was taken into account by the circuit designer, by putting a resistor of merely 100kΩ in series with M1, thereby achieving that the supply voltage was ideally halved again as a result, then this would finally have as effect to halve the net voltage gain at the Drain of M1.

It would also have as effect, to quarter output impedance, which would be desirable from the last of a series of these stages, ending in a realistic load of some kind.

(End of Edit, 7/5/2019, 17h15.)

The Model-Card of the transistor is linked below:

http://dirkmittler.homeip.net/text/NMOS1.mod.txt

To pursue the exact subject of the earlier posting, about Variable-Gain Amplifiers, I also felt that it would be necessary to add to the circuit the components, that would transform it into a variable attenuator. And the following schematic shows how I did that:

(Updated 7/6/2019, 15h10 … )

 

Default_NM_Gain_IF_2

 

(As of 7/4/2019 : )

When the low-frequency voltage ‘Vatten‘ is changed over a range of values, this is a table of amplification factors that results:

 


Atten V     Alpha (-)
3.0         0.171
2.1         0.549
2.0         0.758
1.9         1.211
1.8         2.335
1.7         4.176

 

Obviously, at 1.7V this MOSFET has become inoperative, and left zero possible non-distorted signal-strength. But, if operated between 1.9V and 3.0V, the available factor of modulation is 7.08 .

And this is a link to the Net-List that defines both the Circuit and the Simulation:

http://dirkmittler.homeip.net/text/Default_NM_Gain_IF_2.net.txt


 

(Update 7/6/2019, 15h10 : )

A fact which should be observed, respects the difficulty with which capacitors can be included in a monolithic IC. If the distance between two plates, the dielectric constant of the insulator between those plates – in this case, of silicon dioxide – and the area of both plates are known, the method of computing what the value of the capacitor would be, has not changed from what it was in basic Electricity and Magnetism. What this means is that, if a known capacitance is to be implemented on an IC, then the amount of ‘real-estate’ which that capacitor will take up on the IC will be predictable.

But, if Small-Scale Integration, or Medium-Scale Integration are to be achieved, then, logically, either only capacitor values below some value should be put, or, the number of such capacitors needs to be minimized. Otherwise, capacitors would need to be connected to a pin of the IC as external components.

I would estimate that capacitor values greater than 1nF are generally undesirable, but the only real requirement of my circuit was, that the ratio between C2 and C3 be 1:10. Thus, C1 and C2 can easily be replaced with 100pF, and C3 replaced with 1nF, for an actual IC. Above 10kHz, this should not degrade performance enormously, and above 100kHz, it should not degrade performance at all.

Yet, changing C1, C2 and C3 from their hypothetical values, will of course change the exact numbers that would appear in the table I wrote above, so that it would represent tedium for me, to redo the experiment with capacitance-values more-suited to an IC.

 

It’s natural that in such a circuit, the combination of C1 and R3, as well as the combination of C2 and R2, defines a time-constant, which in this case will act as a first-order high-pass filter both times. This reciprocal of this time-constant is often referred to in Circuit Theory, by the lower-case Omega, which is written (ω). The corner frequency of the filters which result can be computed as follows:

RC-TC_1

So, just off the top of my head I’d say that the corner-frequency resulting from the hypothetical capacitor-values first displayed above was ~160Hz, while, with the values suggested here for IC design, that would become ~1.6kHz.

  • If a higher corner-frequency was desired, i.e., If the stage was also meant to act as a controlled high-pass filter with corner-frequency (F=300kHz), then the way to achieve that could be to reduce C1 and C2 below 100pF. However, stray Gate-capacitance in M1 eventually limits how well this can work, creating an unwanted voltage divider with C1. Also, reducing R3 or R2 is not an option because each time, R2 in this case defines the load placed on the preceding transistor.
  • Similarly, just connecting another capacitor that shunts the Drain of M1 to ground, would achieve a low-pass filter, and then, taking into consideration the output-impedance of the circuit as the new value for (R), which should be (R2/2) for low signal-amplitudes, or, 200kΩ, this time a capacitance could be computed to give a low-pass filter with (F=600kHz). And theoretically, (C=1.33pF) should work. However, this last goal deserves more attention because stray capacitance at the Drain of M1 might come into play at such low capacitor-values, again.
  • Furthermore, even at its corner-frequency, a high-pass or low-pass filter will attenuate the signal-strength by 3db. This observation is important because eventually, a higher-order low-pass filter is supposed to pass the centre-frequency of 450kHz ideally without attenuation, as well as frequencies up to 600kHz without excessive attenuation. Therefore, a higher theoretical corner-frequency (x2) might be considered, for the first-order filter… With NG-SPICE, a shunting capacitor of (0.6pF) seems to give visually appealing results.

These last points could be useful, if (n) of these stages were to complete the IF strip of a radio receiver, which was meant to act as an (n)th-order band-pass filter centred on (IF=450kHz). And in such cases, it may well be that the lower corner-frequency is not well-controlled, while the higher corner-frequency, of each low-pass filter, would be so.

Dirk

 

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