What I find is that in recent years, the term ‘Variable Gain Amplifier’ has changed in meaning, to correspond more to a ‘Variable Attenuation Stage’, after a fixed-gain amplifier. And this seems especially true, when applied to ‘IF Stages’ – ‘Intermediate Frequency Stages’ – Of a radio receiver. I’ve also observed that low-distortion technologies are preferred in recent years, as opposed to the high-distortion technologies that manufacturers were limited to, say, in the 1970s, when ‘AGC’ was first being marketed to consumers.
Yet, even with the technologies that are now available, there are sometimes added constraints. For example, if one wanted the variable-resistance component either to be optical – for lowest distortion – or, for that to be a JFET – easier to implement – then, this component might need to exist externally to an IC, just because the IC itself may be engineered only to allow for two complementary types of transistors, those being, an enhancement-mode N-channel MOSFET and an enhancement-mode P-channel MOSFET. Further, The properties of such MOSFETs can sometimes be inconvenient, in the form of high Threshold voltage, named ‘VT0′, which is the voltage required to make the transistors start to conduct. Practical values of VT0 may be more suited to logic circuits, than to the processing of low-amplitude, analog RF or IF frequencies. A thinner oxide layer for the entire IC can reduce the required VT0.
Yet, the possibility exists for even a MOSFET to operate in ‘Triode Mode’, which is a mode in which it is Not ‘Saturated’. This mode is achieved when:
VDS < VGS – VT0
The problem in trying to reach this mode seems to arise in the fact that if, VT0 is already a higher-than-desired voltage, VGS-VT0 is likely to be a lower-than-desired voltage-range, since VGS is also limited by the supply voltage.
In Triode Mode, a MOSFET effectively behaves like a variable resistor, which decreases in value as the Gate voltage continues to increase.
And so to summarize what form the task might take, to make the Variable Gain Amplifier monolithic with a MOSFET-based IC, I constructed the following, hypothetical diagram, which does not explicitly nail down
what VT0 is supposed to be, nor the supply voltage:
What I seem to have noticed however, in order for the suggested IF stage to work, is that the actual signal should not have a ‘Peak Amplitude’ at the Gate of the last amplifier stage, greater than (0.1V). Yet, the feedback-loop itself, that adjusts attenuation, could play a role in keeping that peak amplitude close to (0.1V).
(Corrected 7/7/2019, 11h05 … )
(As of 7/4/2019 : )
In the diagram above, M1 and M2 would form repeatable stages, and be Saturated, while M3 would operate in Triode Mode. What tends to happen when a MOSFET is Saturated, is that:
IDS = KP(VGS – VT0)2
Where the added property (KP) refers to the (constant) Transconductance of the MOSFET. Because this relates a current to an input voltage squared, for small changes in input voltage, Voltage Gain is the first derivative, multiplied by a constant RD, when RD is constant, and is therefore also proportional to the degree by which the MOSFET is made to conduct – thereby not giving much potential range to the parameter in question:
α = 2 KP RD (VGS – VT0)
The deviation of a parabolic curve from a straight line would state the amount of distortion of low-amplitude signals, and ends up not depending on bias anymore:
KO ~= KP RD ΔVGS / 2
(Last equation corrected 7/7/2019, 11h05.)
(Edit 7/5/2019, 17h35 : )
Doubling (VGS – VT0) of M1 or M2 would have as effect, that IDS quadruples. It would also have as effect, that equal, small changes in Gate Voltage translate into doubled changes in IDS. But, if the increase in bias current was taken into account by the circuit designer, by putting a resistor of merely 100kΩ in series with M1 or M2, thereby achieving that the supply voltage was ideally halved again as a result, then this would finally have as effect to halve the net voltage gain at the Drain of M1 or M2.
It would also have as effect, to quarter output impedance, which would be desirable from the last of a series of these stages, ending in a realistic load of some kind.
(End of Edit, 7/5/2019, 17h35.)
I suppose that the observation I’ve made about this very limited circuit is, that it will only seem useful at greater supply voltages, unless the maximum modulation is supposed to be 8x. And so a further question running though my mind is, ‘What potential is there, in repeating the full set of M1, M2, M3?’ If the maximum usable voltage attenuation (relative to the maximum gain) of one stage is 8x, then the maximum attenuation of 2 stages would be 64x, and that of three stages would be 512x… But one problem with that sort of approach would eventually be, the fact that the maximum signal amplitude, after the first attenuation, needs to be kept lower than (Vatten-VT0). Is it possible that signals so strong, that they effectively need to be attenuated twice, to arrive at a constant output-amplitude, will also require a higher value of (Vatten), as defined above?
Casual inspection would seem to suggest that the answer is Yes, If there is only a total of 2 attenuation stages. The first would bring the signal amplitude down to (0.8V), due to 8x attenuation, which suggests that (Vatten-VT0) was already (0.8V). The second would complete the feedback-loop and bring the signal amplitude down to (0.1V)…
Yet, the possibility of the amplifier stages distorting the signal implies, that signal voltages of (6.4V) should never appear at any MOSFET gate. Therefore, a possible solution to this conundrum presents itself, in that the first attenuation stage could be put near the input of the IF strip, followed by one or more amplifier stages, followed by a second attenuation stage. That way, the signal amplitude presenting itself at the first attenuation stage will be as low as the gain of the following amplifier stages is high, the maximum signal amplitude presenting itself at the gate of last amplifier stage before the second attenuation stage will be 0.8V, and the same feedback-loop that drives the first attenuation stage, will bring the maximum signal amplitude down to 0.1V in the second attenuation stage.
It would be possible to chain 5 gain-stages, with attenuation circuits on the gates of stages 2 and 4.