One of the facts which I’ve been writing about, is that I possess the open-source version of ‘SPICE’, that is named ‘NG-SPICE’, and that this acronym stands for ‘Simulation Program, with Integrated Circuit Emphasis’. The full, associated suite of programs allows me to edit schematic diagrams graphically, but to export ‘Netlists’, so that I can then simulate the circuit – and see if it works.
And one of the facts which I have also been contemplating, is that by default, SPICE will put transistors, which correspond to micron-sized transistors, which will therefore never be able to drive output-loads, from a hypothetical IC, unless an explicit attempt is made, to design output-buffers, which can. These output-amplifiers have as function, that they should merely follow their input voltage, but draw as little current from their respective inputs as possible – that are outputs of other, more interesting ICs – while allowing low load-resistances to be connected to their own outputs, which correspond to plausible external components, such as 100Ω load-resistors.
I had posted an earlier, conceivable design, of such an output-buffer, which had a major flaw, that I also pointed out in the preceding posting: That amplifier could only produce a range of voltages, which was a direct function of what the Gate-Source threshold voltages would be, of the component transistors used. Hence, because I had also specified low-quality, outdated MOSFET transistors with high threshold-voltages, the output-voltage-range, was also modest but reasonable. But, newer transistors will have lower threshold voltages by design, which would, oddly enough, reduce the voltage-range of that amplifier. This would be an important consideration if the transistors were not in fact discrete, but needed to be incorporated onto the IC, where low-threshold-voltage transistors are already standard. Which means, that I needed to design a better output-buffer.
So below is a better output-buffer, schematic:
And these are the SPICE definitions, of the discrete transistors which I decided to base my design on again, both enhancement-mode MOSFETs:
The main disadvantage of this latest design would be, that the transistors which I labeled ‘X2′ and ‘X3′, do in fact conduct current to their combined inputs, which makes the additional transistor ‘X1′ necessary, since this amount of current would already be excessive, to connect to an output, of any pre-existing IC circuits. But then, the advantage goes so far, that ‘X2′ now models a level-shift, which exactly mirrors the level-shift of ‘X4′, and the voltage-level-shift of ‘X3′ now mirrors ‘X5′. There is design beauty in this. But one disadvantage now is, that the Gate-Source threshold-voltage of (1) n-Channel MOSFET (2.2V) plus (1) p-Channel MOSFET (3.2V) gets subtracted from the input-voltage, so that the available voltage-range still suffers, with respect to both the supply, and the input-voltage. Input-voltage now ranges from 5.4V to approximately 12.5V, which is closer to the range of supply-voltages than what the previous circuit allowed, and the resulting output-voltages are graphed below:
(Update 06/20/2018, 0h20 : )
There is another observation which I should add:
In the days of vacuum tubes, ‘transconductance’ was measured in Amperes / Volt, and was therefore given in ‘Mhos’, which were the reciprocal of Ohms. Apparently, in modern days, the transconductance of a MOSFET, also given as its ‘KP’, is in Amperes / Volt2 . This conscious design-decision must follow the real-world behavior of MOSFETs, but makes my earlier Math, of multiplying such a component-property by the series-resistance, to arrive at gain, incorrect. Gate-Source voltage-changes lead to current-changes, but greater Drain-Source voltages, lead to greater current-gain. This is good, because the actual gain of a MOSFET, reduces the apparent capacitance at its Gate.
The low-end output-voltage came into being as follows:
At a certain point in the past, I had stated a value for ‘R1′ and ‘R2′ above, of 8000Ω , to make these significantly greater than ‘R3′. But, the diagram above is an updated diagram, which has taken into account the ‘Afterthought’ which I wrote below…
When ‘X1′ has become non-conductive, ‘R3′ is effectively in series with ‘R1′ and ‘X2′, and in parallel, with ‘X3′ and ‘R2′. This results in a voltage-dividing network, that establishes a lower limit of output-voltages, as a certain fraction of the supply-voltage – in the case of a 15VDC supply, resulting in a minimum output of +2V .
What also follows is, that because ‘R3′ needed to be such a ‘high’, 2kΩ resistor, ‘R1′ and ‘R2′ needed to be increased to 8kΩ . But, because the Gate-Voltages of ‘X4′ and ‘X5′ now follow as the Drain-Voltages of ‘X2′ and ‘X3′, the amount of current that actually flows through ‘X4′ and ‘X5′ in a quiescent state, mirrors the current-level through ‘X2′ and ‘X3′, and is too low for the transistor-types specified. This is also why the output-voltage is so ‘soft’, when a 100Ω load-resistor is connected. ‘X4′ and ‘X5′ are now under-biased. And so we can see that better results, really also require better component-transistors.
Afterthought, 06/18/2018, 14h55 :
Because one assumption about this circuit was, that in order to be operative, all its transistors need to be conductive, it could be argued that output-voltages below +3.2V – the threshold-voltage of the p-Channel transistor – were not to be expected to begin with. Therefore, we’d have nothing to lose, by reducing ‘R1′ and ‘R2′ to 4kΩ . And doing so will double the bias-current flowing through ‘X4′ and ‘X5′, and result in the following transfer function:
(Update 06/20/2018, 0h20 : )
The bigger capacitance-related problem with this circuit :
The Gate-Common capacitance of ‘X4′ and ‘X5′, if it was as high as 20nF, could couple with the values of ‘R1′ and ‘R2′, forming low-pass filters !
And, If ‘X2′ and ‘X3′ were passive, the cutoff-frequency of this low-pass filter could be computed as follows (The reader will probably need to enable scripts from ‘mathjax.org’ to view this) :
So as I would guess, there is virtually no real potential, to connect a 100Ω load to this buffer. Every time we increase the load-resistance by a decade, we will also increase the cutoff-frequency, of the internal low-pass filter which forms, by a decade. Between 10kHz and 1Mhz, this effect was already taking place fully, in the operational-amplifier circuit which I mentioned above, causing that to act as an integrator between those frequencies. However, just adding another stage, which has much-lower-than-unit gain, would not be feasible.
But what SPICE predicts, is actually much more optimistic:
According to NG-SPICE, if the input-voltage is already buffered, then this circuit will continue to follow it well, at 1000x the frequency that arose in the above calculation. This suggests that the load-capacitance presented to the Source of ‘X1′, is already much lower than 20nF .
And so I needed to set up a test for that, using the resistor ‘R4′, which is in-series with the Gate of ‘X1′, and which has a value of 1Ω . I was able to ‘measure’ the (simulated) current through ‘X1′, by measuring the voltage across ‘R4′ as a function of frequency:
Here, it was useful to isolate the imaginary part of the voltage, which should also be useful to determine the Gate-Common capacitance as follows:
In other words, the input-capacitance which forms when all the transistors are active, seems to be on the order of 9.55pF ! It will therefore not interfere with my earlier, ‘fast integrator’.