A Pertinent Question, about Micron-Sized Transistors

If we position two electrodes in free air, 1Centimeter apart, and if we then apply 10000Volts across them, the air’s ability to resist electric current will break down, and an electric arc will appear across it.

Because of this simple observation, the question could (and probably, should) be asked, ‘Can a MOSFET transistor the size of a micron, on an Integrated Circuit, withstand 15Volts of Source-Drain voltage, at all?’

A suggestion to the contrary would be, that 10000Volts /Centimeter, is equal to 1 Volt /Micron. Thus, if the two electrodes were 1Micron apart, and standing free in air, it would take only 1 Volt to cause the air to break down, and for a microscopic arc to appear. Yet, Integrated Circuits are known to exist, which operate at 2 Volts, and which use ‘nanometer technologies’. And so in an effort to answer my own question, I would take two further observations into consideration:

  1. I already recall reading elsewhere, that the breakdown voltage of high-quality, semiconductor silicon, is considerably greater than that of air !
  2. I possess a suite of programs named “SPICE”, which, when performing a Level-8 simulation of MOSFET transistors, only needs to be given the width and the length of a transistor-instance, and which will, on that basis, compute all the other properties of the resulting transistor, making certain assumptions about its design.

This use of SPICE has been commented on, on the following Bulletin-Board:


The part of the thread, which I’ve linked to before, and which I want to call the reader’s attention to, is the part where Holger Vogt writes:

“A 0.18µm process however should run at lower supply voltage, e.g. 1.8-2 V.”

In other words, the OP wrote, that he simulated IC transistors that had a length of 180Nanometers, just by giving the parameters in his Netlists:

W=1u L=0.18u M=1

And what Holger Vogt replied, was that the OP’s supply voltage of 3.3V was a bit high for that, where instead his supply voltage should be no higher than 1.8-2V.

Well Yes, one way to round up 180Nanometers, would be to estimate that it signifies 0.2Microns. But, if a 0.2Micron transistor can operate at 2Volts, then the extrapolation of that would be, that a transistor capable of operating at 15Volts, should have a length of at least 1.5Microns, not 1.0Microns.

And yet, what I did in previous postings, was just to tell ‘NG-SPICE’ to insert a default transistor, and not to give its length or width at all. What I should really do is update my own Model Cards, to specify:

W=1u L=1.5u

Even though the schematics I created seemed to work, I left this part of my assumptions unstated in them. With such a declaration, at least the actual transistors my schematics are to use would be defined. What I need to do, is verify whether the simulations will still work, given plausible specifications of that type. But, as I’m blogging this, the time is 22h30, and I need to get some sleep. I don’t have time to perform this test right now, and will get back to it when I have time.

(Update 06/17/2018, 8h45 : )

I’ve just updated the Model Cards, and found that the reloaded simulations ran, approximately as before.

When a circuit is properly designed, then its output-characteristics will depend less, on the Source-Drain properties of any one transistor, and more, on the arrangement of transistors, as well as on feedback, such as due to feedback-resistors. The operational-amplifier circuit I had designed before, only had one transistor connected in such a way, that it could have defined the output-curve by itself, and in the latest diagram of that op-amp, that transistor was labeled ‘M4′ . It was meant by me to act as a fast integrator, together with ‘C2′ . But, because even this transistor had a resistor connected between the supply-voltage and its Drain, the value of which was 40000Ω , this resistor still did more to define the overall transfer-function, than the Source-Drain spacing of ‘M4′ did.


One default that did change the simulation however, was the ‘Gate Oxide Thickness‘, which helps define all the threshold voltages. Because any modifications of ‘TOX’ had radical effects on my circuit, what I did was to look up the default in the BSIM3, that default being ’15Nanometers’, and I inserted that into my Model Card, to make it explicit. Doing so restored the exact outcome of the simulations.

But then a similar question could be asked, about whether such a thin Oxide Layer would also (not) break down at +15V. It’s harder for me to gauge the answer to that question, even though I know, that the breakdown voltages for Silicon Dioxide, are even higher than those for pure Silicon. I do know:

  • When a MOSFET is exposed to static electricity, because it has not been inserted into a circuit, this will destroy its gate,
  • Static Electricity actually consists of thousands of Volts at very low current, which does not in itself imply that the gate will break down at +15V,
  • Actual “90 Nanometer Technology” will adopt 1Nanometer Oxide Thickness (see WiKi-Link above), which would be 15x narrower than the ‘NG-SPICE’ default. Hence, if the Nanometer Technology can actually withstand gate voltages of +1V, then the defaults should go as high as +15V. This suggests that a gate voltage of +15V will be tolerated, because 90 Nanometer Technology is already operated at 1.8VDC supply-voltage.

In my own experiments, 15Nanometer Gate Oxide Thickness is now explicit, where before, it was implicit.



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