Variable-gain amplifier, with good frequency response including 4MHz.

In an earlier posting, I had described a variable-gain amplifier that could be etched into a monolithic IC. But, that circuit had as its main drawback, that it would only seem to work well at a centre-frequency of ~500kHz, while most circuit designs expect Megahertz frequencies, when working in the analog domain.

The diagrams in this posting have been tested using the open-source simulation software named ‘NG-Spice’.

In order to achieve Megahertz frequency response, I needed to discover a little trick, which professional circuit designers – aka Electrical Engineers – probably already know. What the previous circuit had done, was to set (R4) to 32kΩ, while setting (R1) to 40kΩ. The reason I had done this was, the old-fashioned idea that the pull-up resistor of the amp should bisect the supply voltage, with the main transistor in series, in order to achieve maximum gain. Yet, the bias voltages were more likely to be in the vicinity of 1.8V. Thus, (R4) would bias (M2) to conduct a certain amount of current, and because both (M1) and (M4) are in saturation mode, they will both conduct the same amount of bias current between their Source and Drain, due to the resulting bias voltage at both Gates. Yet, that amount of current would cause a 1.5V voltage-drop through (R1), while causing a 1.2V voltage-drop through (R4).

Hence, with 2 voltage-levels, it was necessary to put a coupling capacitor, which in turn is a hassle on an IC.

The trick seems to be, that (R1) and (R4) can be set to the same value, so that the DC component of the Drain voltage, will equal the bias voltage. That way, as many circuits as needed can just be chained, with equal bias voltages, and No Coupling Capacitors. The bias voltage I now obtain, is (1.857V).

Additionally, I retuned the circuit, by reducing the width of (M1) and (M2) from 100μM to 25μM, which in turn reduces Drain-to-Gate capacitance, which in turn would hinder good, high-frequency response. (M4) now also has a width of 25μM, so that it can be biased in a matching way.

Yet, with the transistors so small, the output would need to be protected by that additional transistor (M4), so that to connect minor loads to it will not collapse the functioning of the main stage.

The result was, that with a control voltage of (2.0V) and a frequency of 4MHz, a gain of almost +40dB was obtained, while with a control voltage of (0.0V), a signal drop, and indeed inversion of the phase was obtained, because (M3) just bypassed (M1).

The following is the Netlist of the (2.0V) simulation:

http://dirkmittler.homeip.net/text/Default_NM_Gain_IF_13.net.txt

And these are the Modelcards of the transistors used:

http://dirkmittler.homeip.net/text/NMOS2.mod.txt

http://dirkmittler.homeip.net/text/PMOS2.mod.txt

 

This is an image of the schematic:

 

Default_NM_Gain_IF_13

 

(Updated 5/29/2021, 12h15… )

(As of 5/29/2021, 0h20: )

And, these are screen-shots, of the low-gain, followed by the high-gain frequency response curves:

 

Screenshot_20210528_233251 Screenshot_20210528_233745

 

The fact should also be noted that, even though the schematic indicates a coupling capacitor at the input, in the form of (C1), which in turn causes the droop in gain at the lowest frequencies, this capacitor is fictitious. When connecting such circuits to each other on a chip, this capacitor would not be inserted.

 

Note:

The effective output impedance of this circuit is 72kΩ.


 

(Update 5/29/2021, 4h10: )

In order for this circuit to be non-distorting, (M3) needs to keep operating in triode mode, contrarily to how all the other transistors are operating in saturation mode. This requires that (VDS < (VGS – VT0)). In order to achieve that, (VT0) must first be determined. Since a control voltage of (0.35V) starts to affect gain, it would seem to follow that (VT0 ~= 1.5V).

Well, if the control voltage is kept below (0.25V) during operation, then (VGS – VT0) will remain greater than (0.1V). Under those conditions, the Gain of (M1) drops to -1.0 such that (VDS) belonging to (M3) will reach 1.5 times the input amplitude. Given the voltage divider which forms between (R2) and (R3), this means that the input amplitude should not exceed 0.0667V, when the control voltage is in fact (0.25V).

Clearly, such a stage would need to be inserted at the beginning of a radio’s IF strip, not, near the end.

The following screen-shot shows, what the actual overall gain will be, at (Vcontrol == 0.25V):

 

Screenshot_20210529_032139

 

As the reader may notice, the overall gain will remain more constant over the frequency range, but, at a more modest +23dB.


 

(Update 5/29/2021, 11h10: )

A valid question which the reader might have next could be, ‘What can be done, to achieve control voltages in that range easily?’ And one answer could present itself, in the following schematic:

 

Default_NM_Gain_IF_16

 

In other words, (M5) and (R6) can be added as shown, the new control voltage could result as a positive function of how strong the output signal is, and then, the only recognizable behaviour of the circuit will remain, to use the resulting, negative feedback loop to keep the new control voltage at (1.18V). At that point, the feedback loop will have high gain, so that it would be up to the reader, actually to slow it down, in order to make it stable.

This should result from an output signal-voltage no stronger than ±0.5V, just to keep (M3) functioning in triode mode. And in that configuration, the input voltage of the circuit should be no higher than (±0.25V).

 

(Update 5/29/2021, 12h15: )

If the second circuit suggested in this posting is fed an input signal voltage of (±0.25V), then the voltage it will apply to the Gate of (M3) will be (0.16V), so that the (VGS – VT0) of (M3) will become (0.19V). Yet, its (VDS) will then be (0.175V), suggesting that distortion will not set in.

However, if the second circuit suggested in this posting is fed an input signal voltage of (±0.5V), then the voltage it will apply to the Gate of (M3) will be (0.115V), so that the (VGS – VT0) of (M3) will become (0.235V). Yet, its (VDS) will then be (0.3V), suggesting that distortion will set in.

And, if the second circuit suggested in this posting is fed an input signal voltage of (±0.025V), then the voltage it will apply to the Gate of (M3) will be (0.28V), so that the (VGS – VT0) of (M3) will become (0.07V). Yet, its (VDS) will then be (0.0625V), suggesting that distortion will not set in.

 

Enjoy,

Dirk

 

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